DAC80504 datasheet(25/50 Pages) TI2

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DAC80504, DAC70504, DAC60504

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SBAS871C – AUGUST 2017 – REVISED JANUARY 2019

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8.4 Device Functional Modes

8.4.1 Stand-Alone Operation

A serial interface access cycle is initiated by asserting the CS pin low. The serial clock SCLK can be a

continuous or gated clock. SDI data are clocked on SCLK falling edges. A regular serial interface access cycle is

24 bits long with error checking disabled and 32 bits long with error checking enabled, thus the CS pin must stay

low for at least 24 or 32 SCLK falling edges. The access cycle ends when the CS pin is de-asserted high. If the

access cycle contains less than the minimum clock edges, the communication is ignored. If the access cycle

contains more than the minimum clock edges are present, only the last 24 or 32 bits are used by the device.

When CS is high, the SCLK and SDI signals are blocked and the SDO pin is in a Hi-Z state.

In an error checking disabled access cycle (24-bits long) the first byte input to SDI is the instruction cycle which

identifies the request as a read or write command and the 4-bit address to be accessed. The following bits in the

cycle form the data cycle, as shown in Table 2.

Table 2. Serial Interface Access Cycle

BIT

FIELD

DESCRIPTION

Identifies the communication as a read or write command to the addressed register. R/W = 0 sets a

write operation. R/W = 1 sets a read operation.

22:20

Reserved

Reserved bits. Must be filled with zeros.

19:16

A[3:0]

15:0

DI[15:0]

Data cycle bits. If a write command, the data cycle bits are the values to be written to the register with

address A[3:0]. If a read command, the data cycle bits are don’t care values.

A read operation is initiated by issuing a read command access cycle. After the read command, a second access

cycle must be issued to get the requested data, as shown in Table 3. Data are clocked out on SDO pin either on

the falling edge or rising edge of SCLK according to the FSDO bit in the CONFIG register.

Table 3. SDO Output Access Cycle

BIT

FIELD

DESCRIPTION

Echo RW from previous access cycle.

22:20

Reserved

Echo bits 22:20 from previous access cycle (all zeros).

19:16

A[3:0]

Echo address from previous access cycle.

15:0

DO[15:0]

Readback data requested on previous access cycle.

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