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VNF9D5F Datasheet(PDF) 54 Page - STMicroelectronics

Part # VNF9D5F
Description  2-channel high-side driver with STi²Fuse protection for automotive power distribution applications
PDF  108 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

VNF9D5F Datasheet(HTML) 54 Page - STMicroelectronics

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•
A conversion of selected channels is done based on the information stored at the end of the stack (see
Figure 25).
•
After the reset of the device or when no channels are active, the conversion of the Frame temperature
sensor is done continuously.
When the conversion of a channel_x has to start, the channel_x is moved to the end of the stack while the other
remaining channels are moved up.
Figure 25. Channel's sequence internal stack
0
1
2
3
4
5
T
0
1
2
4
3
5
T
0
1
2
4
5
T
3
0
1
2
4
T
3
5
0
1
2
4
5
T
3
0
1
2
4
T
3
5
Elaboration of new stack
based on the conversion
request and priority
management
Conv_ch3
NEXT_STACK = STACK
NEXT_STACK = STACK
Channel 6 (Tframe)
is converted
Channel 5 is converted
Bottom position is at
highest Priority
Channel 3 is converted
Conv_ch5
Time
No Conv
Tframe is
Converted
Next Stack
Stack
Next Stack
Stack
Next Stack
Stack
5.1.3
Registers
The results of the digital conversion are stored in the two dedicated registers, used for the digital conversion of
the output current and case sense temperature respectively:
•
ADCxSR (address from 28h to 29h) - Digital Outputx current (one register x channel).
•
ADC9SR (address 31h) - Digital case temperature sensor voltage sense register.
Table 38. Registers
Register
name
Bit 15, 14 Bit 13..4
Bit 3
Bit 2
Bit 1
Bit 0
ADCxSR
28h to 29h
Reserved
Digital Value of OUTx
current
Reserved
SOCRx
Possibility to
control the Outx
state (Read only)
UPDTSR
Updated status bit. It is set when
value is updated and cleared
when register is read
Parity
ADC9SR
31h
Reserved
Digital Value of case
temperature sensor
voltage
Reserved Reserved
UPDTSR
Updated status bit. It is set when
value is updated and cleared
when register is read
Parity
5.1.4
Synchronous, asynchronous mode
Normal mode
The ADC conversion can work in 4 different sampling modes (stop, start, continuous or filtered) according to the
Table 39. Two bits per channel “SPCR1” and “SPCR0” allocated in the Output Configuration Register
“OUTCFGRx”, allow 4 different sampling modes:
VNF9D5F
Diagnostic
DS13946 - Rev 8
page 54/108



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