VNF9D5F datasheet(57/108 Pages) STMICROELECTRONICS

57 / 108 page

Synchronous mode in DC condition

This mode (PWM with 100% duty cycle) is equivalent to the asynchronous mode.

Table 40. ADC Configurations registers

SOCrx DIx DutyCrx SPCR1, 0

Conversion Mode

Feedback type

Synchronous triggered by falling edge on the internal PWM signal Output current

Synchronous triggered by rising edge on the internal PWM signal Output current

Asynchronous with continuous sampling

Output current

Asynchronous with continuous sampling and digital LP filter

Output current

(Fail Safe mode)

Asynchronous with continuous sampling

Output current

Tframe conversion

(Always lower priority than current sampled modes)

Tframe sensor voltage

5.2

Integrated LP (progressive average) filter

In asynchronous mode, when the filtered mode is selected through the dedicated bits “SPCR1 = 1” and “SPCR0 =

1”, the integrated LP filter is activated. This component will filter the data coming from the ADC conversion

reducing the effect of random noise coming from the analog Current Sense amplifier.

Features of the integrated LP filter:

•

1st order decimating filter on 16 samples.

•

1st result after 1 sample with progressive averaging of 16 successive samples.

dataN = dataN−1*1516+datai/16

(1)

•

Continue to accumulate samples during PWM with SOCR = 1.

•

Keep digitalized value when the channel is turned off.

VNF9D5F

Diagnostic

DS13946 - Rev 8

page 57/108

VNF9D5F Datasheet(PDF) 57 Page - STMicroelectronics