VNF9D5F datasheet(26/108 Pages) STMICROELECTRONICS

26 / 108 page

Note:

X = do not care.

0xBF - clear all status registers (RAM access)

When an OpCode ‘10’ (read and clear operation) at address b’111111 is performed.

Table 22. Clear all status registers (RAM access)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Command

OC1

OC0

Address

DATA1

DATA2

Note:

X = do not care.

Note:

Reset value = the value of the register after a power on.

Default value = the default value of the register. Currently this is equivalent to the reset value.

Cleared register = explicitly read and clear of the register, if it is not write-protected.

4.3

The device contains a set of RAM registers used for device configuration, the device status and ROM registers for

device identification. Since ST-SPI is used, Global Status byte defines the device status, containing fault

information.

4.3.1

Global status byte description

The data shifted out on SDO during each communication starts with a specific byte called global status byte. This

one is used to inform the microcontroller about global faults which can happen at channel-side level (that is, like

thermal shutdown...) or on the SPI interface (like watchdog monitoring timeout event, communication error, ...).

This specific register has the following format:

Table 23. Global Status Byte (GSB)

MSB

LSB

GSBN

RSTB

SPIE

TSD/PL

ITLOFF

LOFF

TCASE

Table 24. Global Status Byte

Bit

Name

Reset

Content

Global status bit not

(GSBN)

The GSBN is a logically NOR combination of Bit 0 to Bit 6. This bit can also be used as

Global Status Flag without starting a complete communication frame as it is present

directly after pulling CSN low.

Reset bit (RSTB)

The RSTB indicates a device reset. In case this bit is set, all internal Control Registers

are set to default and kept in that state until the bit is cleared.

The reset bit is automatically cleared by any valid SPI communication

SPI error (SPIE)

The SPIE is a logical OR combination of errors related to a wrong SPI communication

(SCK count and SDI stuck at errors).

The SPIE bit is automatically set when SDI is stuck at High or Low. The SPIE is

automatically cleared by a valid SPI communication.

VNF9D5F

SPI functional description

DS13946 - Rev 8

page 26/108

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