VNF9D5F datasheet(67/108 Pages) STMICROELECTRONICS

67 / 108 page

Parallel mode

Parallel mode may be enabled by setting the corresponding OTP bit to 1 (by default, it is disabled).

During parallel mode CH0 and CH1 are driven by the only DIx associated to CH0 (depending on DIx assignment

logic configured through OTP).

When this bit is set high, CH1 control register bits are automatically linked to CH0 values, thus CH1 is

programmed exactly as CH0. This means that:

•

Every control command addressed to CH0 is reflected also to CH1.

•

Every control command addressed to CH1 is ignored.

•

Every configuration set addressed to CH0 is reflected also to CH1.

•

Every configuration set addressed to CH1 is ignored.

•

LED mode is disabled for CH0 and CH1.

•

Each channel protection is separated and active, and their triggering impacts both channels (for instance, a

thermal shutdown event on CH1 turns off CH0 and CH1 at the same time).

•

Each channel diagnostic stays separate on their own registers.

•

Current sense architectures stay separate as well as ADC conversions.

•

Harness protection is active, merged, and adapted to parallel mode:

–

tNOM as per the one programmed for CH0.

–

INOM setting for both channels come from CH0 one (the INOM table is automatically doubled).

Parallel mode cannot ensure double energy capability due to the natural difference between the clamp structures.

Thus, an external free wheeling diode is suggested when enabling this function. For further information refer to

the related 'Application note'.

When parallel mode is selected, only the bulb functionality is available (LED mode is internally disabled, whatever

is the logic state of this bit).

VNF9D5F

Parallel mode

DS13946 - Rev 8

page 67/108

VNF9D5F Datasheet(PDF) 67 Page - STMicroelectronics