ADF5611BCCZ datasheet(18/48 Pages) AD

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Data Sheet

ADF5611

THEORY OF OPERATION

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Rev. 0 | 18 of 48

INTRODUCTION

A PLL is a complex feedback system that can conceptually be

considered a frequency multiplier. The system multiplies the refer-

ence frequency input at XREFP and outputs a higher frequency at

RFOUT (single-ended output) or at PDIV_OUT or NDIV_OUT (dif-

ferential output). The PFD, charge pump, output divider, feedback

divider, VCO, and external loop filter form a feedback loop to accu-

rately control the output frequency (see Figure 43). When operating

in integer mode, the reference divider sets the frequency resolution.

When operating in fractional mode, the fractional-N divider sets the

frequency resolution.

Figure 43. PLL Loop Diagram

OUTPUT FREQUENCY

When the loop is locked, the fVCO (in Hz) produced at the output of

the VCO is determined by the reference frequency (fREF), reference

division factor (R_DIV), and the N values given by the following

equation:

fVCO= fPFD×N

(1)

where the Feedback Counter N is given by the following:

N=NINT+ FRAC1WORD+FRAC2WORD

MOD2WORD

MOD1WORD

(2)

where:

INT is a 20-bit integer value.

FRAC1WORD is the numerator of the primary modulus (0 to

33554431).

FRAC2WORD is the numerator of the 24-bit auxiliary modulus (0 to

16777215).

MOD2WORD is the programmable, 24-bit auxiliary fractional modu-

lus (2 to 16777215).

MOD1WORD is a 25-bit primary modulus with a fixed value of 225 =

33554432

The fPFD is expressed by the following:

fPFD=fREFRDIV

(3)

The output frequency, fRFOUT, produced at the output channel

RFOUT is given by the following:

fRFOUT= 2 × fVCO

(4)

While the differential output frequency, fDIVOUT, produced at

PDIV_OUT and NDIV_OUT

is expressed by the following:

fDIVOUT= 2×fVCO

2RFOUT_DIV

(5)

RFOUT_DIV refers to the clock output divider, which can divide the

RFOUT from 1 to 128, following a power of 2 progression, see the

RF Output Divider section.

Output Frequency Calculation Procedure

The following is a worked example for a fractional mode fRFOUT

using the formulas in the Output Frequency section.

For fRFOUT = 12.1234GHz and a channel spacing (fCHSP) of 1Hz,

where fREF = fPFD = 100MHz and the reference divider is set

to divide by 1 (R_DIV = 1), the output frequency is within the

fundamental VCO frequency range (fVCO).

The steps to calculate all N-divider component values are outlined

as follows:

1. Calculate the overall N value required based on the fRFOUT and

fPFD provided as follows:

N = fRFOUT2×fPFD

(6)

N= 12.1234GHz

2×100MHz

=60.617

(7)

2. Separate the NINT and NFRAC components as follows:

NINT = INT(N) = 60

(8)

NFRAC= N ‐ NINT = 0.617

(9)

3. Calculate the FRAC1WORD as follows:

NFRAC1WORD = NFRAC×MOD1WORD (10)

Where MOD1WORD is a fixed value of 225 = 33554432.

NFRAC1WORD = 0.617 × 33554432 =

20703084.544

(11)

FRAC1WORD=

INTNFRAC1WORD = 20703084

(12)

FRAC2WORD and MOD2WORD are only required if

NFRAC1WORD is not an integer number. If NFRAC1WORD is

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