ADF5611BCCZ datasheet(23/48 Pages) AD

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Data Sheet

ADF5611

THEORY OF OPERATION

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Rev. 0 | 23 of 48

MUXOUT

The MUXOUT bits (Register 0x02B, Bits[7:4]) provide the user

with access to various internal nodes. A common application of

the MUXOUT bits is to serve as an extra lock status output or

to debug PLL-related issues during the hardware and software

development stages of a project. The MUXOUT bits and the SDO

pin have a shared function on the SDO Pin (Pin 19). Refer to Table

12 to access the MUXOUT bits on the SDO pin. In 3-wire mode

(SDO_ACTIVE = 0), set EN_MUXOUT (Register 0x2B, Bit 3) to 1

to output the MUXOUT data. In 4-wire mode (SDO_ACTIVE = 1),

set EN_MUXOUT to 0 to allow SPI data to be read from the device

during a SPI read operation. The CMOS_OV bit (Register 0x035,

Bit 5) determines if the logic high level for the SDO or SDIO pins is

3.3V or 1.8V. See Table 12 for the different SDO pin configurations.

Table 12. SDO Pin State

SDO_ACTIVE,

EN_MUXOUT

SDO Pin State

SDO pin inactive

MUXOUT signal

SDO data

MUXOUT signal

Temperature Sensor

The temperature sensor is composed of an 8-bit ADC, which

measures the proportional to absolute temperature (PTAT) voltage

with respect to the reference voltage (VREF) of a bandgap. The

purpose of the temperature sensor is to measure changes in the die

temperature and not the absolute junction temperature. The ADC

clock can be generated from the reference clock (normal operation)

or the SCK (test mode) that is configured in ADC_CLK_TEST_SEL

bit (Register 0x037, Bit 0). Configuring the ADC_CLK_TEST_SEL

to 1 (SCK) allows ADC conversion while all other blocks are

inactive. In this configuration, the temperature of the chip is solely

affected by the ADC. For normal operation, ADC_CLK_TEST_SEL

set to 0. The maximum ADC clock frequency is 400kHz, and the

ADC_CLK_DIV register (Register 0x036, Bits[7:0]) is used to set

the division factor that divides the actual clock sent to the ADC.

To initialize ADC measurement, program the registers of the

ADF5611 as shown in Table 13. An ADC conversion requires 17

clock cycles to complete. The ADC_BUSY readback bit (Register

0x048, Bit 2) monitors the conversion status. During a conversion,

ADC_BUSY reads back to 1, and when the conversion is complete,

ADC_BUSY reads back to 0. Measurements are then recorded in

the 8-bit CHIP_TEMP register bit fields (Register 0x04A, Bits[7:0]

and Register 0x04B, Bit 0). The value read back in Register 0x04A

represents the junction temperature in degrees Celsius. The MSB

(Bit 8) in Register 0x04B indicates positive or negative temperature,

that is, when Bit 8 = 1, the temperature read back is negative.

Table 13. ADC Register Setup

Bit Fields

Value

EN_DNCLK, EN_ADC

EN_ADC_CLK, ADC_ST_CNV, and EN_ADC_CNV

PD_ADC

Double Buffering

Double buffering refers to a main and subordinate configuration for

the bit fields detailed in Table 14.

Only the subordinate bit fields control the actual state of the

ADF5611. When double buffering is enabled for a bit field, the SPI

only writes to the main bit field. The subordinate bit field retains its

previous value until a register write is sent to Register 0x010. After

writing to Register 0x010, all the main bit fields are automatically

loaded to their respective subordinate bit fields. Writing to Register

0x010 also starts the autocalibration of the VCO (see the Standard

Power-Up and Initialization Sequence, Automatic VCO Calibration

section), which allows the user to update several bit fields that

change the output frequency of the ADF5611 and starts a new VCO

calibration on the same register write. When double buffering is

disabled, the SPI writes directly to the subordinate bit field.

Table 14. Double Buffer Enabled Bit Fields

Double Buffer Enabler Bits

Double Buffered Bit Fields

Not Applicable, Always Enabled

N_INT, R_DIV, FRAC1WORD,

FRAC2WORD, MOD2WORD, CP_I

RFODIV_DB (Register 0x02C, Bit 7)

RFOUT_DIV

O_VCO_DB (Register 0x031, Bit 7)

M_VCO_CORE, M_VCO_BAND,

M_VCO_BIAS

DEL_CTRL_DB (Register 0x033, Bit 7)

BLEED_I, BLEED_POL

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