ADF5611BCCZ datasheet(22/48 Pages) AD

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Data Sheet

ADF5611

THEORY OF OPERATION

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Rev. 0 | 22 of 48

the desired PFD cycles on the LD_COUNT bits (Register 0x029,

Bits[4:0]). Five loop filter time constants can be used as an initial

approximation of the needed number of PFD cycles, as shown in

the following equation:

PFD Cycles = 52 × π × LFBW ×fPFD

where:

LFBW is the loop filter bandwidth

fPFD is the PFD frequency

Table 9. LD_COUNT Programming

LD_COUNT[4:0]

PFD Cycles

131

195

259

387

515

771

1027

1539

2051

3075

4099

6147

8195

12291

16387

24579

32771

Figure 52. Lock Detector Timing, Bleed Current Disabled

Table 10. Lock Detector Timing, Bleed Current Disabled

Region

Absolute Phase

Difference at PFD

Lock Detector State

>tLDWIN

Low

<tLDWIN

Low, counts PFD cycles

Table 10. Lock Detector Timing, Bleed Current Disabled (Continued)

Region

Absolute Phase

Difference at PFD

Lock Detector State

High, greater than or equal to the desired

PFD cycle count

<tLDWIN

High

>tLDWIN

Low (immediately)

When the charge pump bleed current is enabled, a phase offset is

applied to the PFD inputs. This phase offset, tIDEL, is proportional to

the amount of bleed current. Region 3 and Region 4 in Figure 52

and Figure 53 highlight the PFD phase difference the PLL settles

to when the charge pump bleed current is disabled or enabled,

respectively.

Figure 53. Lock Detector Timing, Bleed Current Enabled

For proper operation of the lock detector, the absolute value of tIDEL

must be less than tLDWIN. The user sets the phase difference lock

window time (tLDWIN) for a valid lock condition on the LDWIN_PW

bits (Register 0x029, Bits[7:5]). Configure the LDWIN_PW bits to

1 for integer mode and to 3 for fractional mode. All other bit field

combinations are not applicable.

Table 11. LDWIN_PW Programming

LDWIN_PW [7:5]

Mode of Operation

001

Integer mode, 100MHz maximum PFD

011

Fractional mode, 100MHz maximum PFD, RF ≥ 3.65GHz

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