ADF5611BCCZ datasheet(20/48 Pages) AD

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Data Sheet

ADF5611

THEORY OF OPERATION

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Figure 46. Common Clock Interface: Single-Ended Clock with End

Termination (ZO = 50 Ω)

Figure 47. Output Interface Schematic

Feedback Divider (N)

The feedback divider provides a division ratio in the PLL feedback

path. The division ratio consists of a 20-bit N_INT (Register 0x010

to Register 0x012), a 25-bit FRAC1WORD (Register 0x012 to Reg-

ister 0x015), a 24-bit FRAC2WORD (Register 0x017 to Register

0x019), and a 24-bit MOD2WORD (Register 0x01A to Register

0x01C) bit field values that this divider comprises together with the

fixed modulus MOD1WORD (225).

Reference Input

The reference signal of the PLL is input through XREFP, which

operates as a single-ended input. This high impedance input is self

biased and requires AC-coupling (refer to Figure 48 for a simplified

schematic of the reference input stage). The reference signal input

on the XREFP is enabled by configuring the PD_RDIV bit (Register

0x027, Bit 6) to 0. In this case, SW1 and SW2 are closed, and SW3

is open.

The slew rate of the input reference signal significantly affects

the performance. The device is functional with signals as low as

0.4V p-p amplitude. However, to achieve optimal performance and

the in-band phase noise performance of the ADF5611, apply a

continuous sine-wave signal or a square-wave signal with a slew

rate of at least 500V/µs. Achieving this slew rate with sinusoidal

waves requires high amplitudes and may not be possible at low

frequencies. For a frequency input of 10MHz, a square wave is

required. A high performance square wave signal with a high slew

rate is recommended as the reference input signal to achieve

the best performance. See Figure 49 for reference input signal

requirements and interfacing.

Figure 48. Reference Input Stage

Figure 49. Reference Input Source

Reference Divider

The reference path R divider, R_DIV (Register 0x01F, Bits[7:0] and

This divider is used to reduce the frequency seen at the PFD, and

its divide ratio (R) can be set to any integer from 1 to 16,383,

inclusive. Use the R_DIV bits to directly program the R divide ratio.

Phase and Frequency Detector (PFD)

The PFD, in conjunction with the charge pump, produces source

and sink current pulses proportional to the phase difference be-

tween the outputs of the reference divider or reference doubler

and feedback divider. These source and sink pulses are required

to phase lock the loop, forcing a phase alignment at the inputs of

the PFD. The PFD includes a fixed delay element that sets the

width of the antibacklash pulse. This pulse ensures that there is no

dead zone in the PFD transfer function and provides a consistent

reference spur level. Set the phase detector polarity to positive on

this device because of the positive tuning of the VCO. See Figure

50 for a simplified schematic of the PFD.

Figure 50. Simplified PFD Schematic

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