ESMT

AD22650

Elite Semiconductor Memory Technology Inc.

Publication Date: Jan. 2018

Revision: 1.8

3/24

Functional Block Diagram

LINP

LINN

OUTL

EN

PVSS

CN

SGND

RINP

RINN

OUTR

UVP

PVDD

CP

PGND

Charge Pump

Under

Voltage

Protection

Depop

Circuit

Over

Temperature

Protection

Available Package

Package Type

Device No.

Θ

ja (℃/W)

(1)

Θ

jc (℃/W)

(2)

TSSOP-14

AD22650

100

32

(1)

Θ

ja is measured at room temperature (TA=25℃), natural convection environment test board, which is constructed with a thermal efficient,

2-layers PCB. The measurement is tested using the JEDEC51-3 thermal measurement standard.

(2) Θ jc represents the heat resistance for the heat flow between the chip and package’s top surface.

Marking Information

AD22650

Line 1 : LOGO

Line 2 : Product No.

Line 3 : Tracking Code

Line 4 : Date Code

ESMT

AD22650

Tracking Code

Date Code