DAC38RF80IAAV datasheet(39/160 Pages) TI2

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PLL, a high loop bandwidth up to 60 MHz is more appropriate. Note that the use of ultra-high loop bandwidth

setting is not recommended for PLL multiply factor of less than 8.

A free running clock output is available when field ENDIVCLK in register SRDS_PLL_CFG (8.5.85) is set high. It

runs at a fixed divided-by-80 of the PLL output frequency and can be output on the ALARM pin by setting field

DTEST to “0001” (lanes 0 – 3) or “0010” (lanes 4 – 7) in register DTEST (8.5.76).

7.3.4 SerDes Equalizer

All channels of the DAC38RFxx incorporate an adaptive equalizer, which can compensate for channel insertion

loss by attenuating the low frequency components with respect to the high frequency components of the signal,

thereby reducing inter-symbol interference. Figure 7-9 shows the response of the equalizer, which can be

expressed in terms of the amount of low frequency gain and the frequency up to which this gain is applied (that

is, the frequency of the ’zero’). Above the zero frequency, the gain increases at 6 dB/octave until it reaches the

high frequency gain.

108

414

Log10MHz

-6.3

Frequency

Figure 7-9. Equalizer Frequency Response

The equalizer can be configured through fields EQ and EQHLD in register SRDS_CFG1 (8.5.86). Table 7-6 and

Table 7-7 summarize the options. When enabled, the receiver equalization logic analyzes data patterns and

transition times to determine whether the low frequency gain should be increased or decreased. The decision

logic is implemented as a voting algorithm with a relatively long analysis interval. The slow time constant that

results reduces the probability of incorrect decisions but allows the equalizer to compensate for the relatively

stable response of the channel. The lock time for the adaptive equalizer is data dependent, and so it is not

possible to specify a generally applicable absolute limit. However, assuming random data, the maximum lock

time will be 6x106 divided by the CDR activity level. For field CDR in register SRDS_CFG1 (8.5.86) = 110, the

activity level is 1.5 x 106 UI.

When EQ = 0, finer control of gain boost is available using the EQBOOST IEEE1500 tuning chain field, as

shown in Table 7-8.

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DAC38RF80, DAC38RF83, DAC38RF84

DAC38RF85, DAC38RF90, DAC38RF93

SLASEA3D – DECEMBER 2016 – REVISED DECEMBER 2023

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DAC38RF80IAAV Datasheet(PDF) 39 Page - Texas Instruments