WM8941GEFLSLASHV datasheet(26/96 Pages) WOLFSON

26 / 96 page

WM8941

Pre Production

PP, Rev 3.3, December 2007

The ADC is enabled by the ADCEN register bit.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Power

management 2

ADCEN

0 = ADC disabled

1 = ADC enabled

Table 11 ADC Enable

The polarity of the output signal can also be changed under software control using the ADCPOL

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R14

ADC Control

ADCPOL

0=normal

1=inverted

Table 12 ADC Polarity

SELECTABLE HIGH PASS FILTER

A selectable high pass filter is provided. To disable this filter set HPFEN=0. The filter has two

modes controlled by HPFAPP. In Audio Mode (HPFAPP=0) the filter is first order, with a cut-off

frequency of 3.7Hz. In Application Mode (HPFAPP=1) the filter is second order, with a cut-off

frequency selectable via the HPFCUT register. The cut-off frequencies when HPFAPP=1 are shown

in Table 14.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

HPFEN

High Pass Filter Enable

0=disabled

1=enabled

HPFAPP

Select audio mode or application mode

0=Audio mode (1

st order, fc = ~3.7Hz)

1=Application mode (2nd order, fc =

HPFCUT)

R14

ADC Control

6:4

HPFCUT

000

Application mode cut-off frequency

See Table 14 for details.

Table 13 ADC Filter Select

WM8941GEFL/V Datasheet(PDF) 26 Page - Wolfson Microelectronics plc

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