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MAXQ3180-RAN+ Datasheet(PDF) 16 Page - Maxim Integrated Products |
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MAXQ3180-RAN+ Datasheet(HTML) 16 Page - Maxim Integrated Products |
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16 / 48 page ![]() Low-Power, Multifunction, Polyphase AFE 16 ______________________________________________________________________________________ Optionally, a cyclic redundancy check (CRC) byte can be appended to each transaction. For write commands, the CRC byte is sent by the master, and for read com- mands the CRC byte is sent by the MAXQ3180. The CRC mode is enabled when the CRCEN bit is set to 1 in STATUS0 register. Otherwise, the MAXQ3180 assumes no CRC byte is used. The 8-bit CRC is calcu- lated for all bytes in a transaction, from the first com- mand byte sent by the master through the last data byte excluding sync bytes, using the polynomial P = x8 + x5 + x4 + 1. If the transmitted CRC byte does not match the calculated CRC byte (for a write command), the MAXQ3180 ignores the command. The length of the transfer is defined by the first com- mand byte and the status of the CRCEN bit in the STATUS0 register. There is no special synchronization mechanism provided in this simple protocol. Therefore, the master is responsible for sending/receiving the cor- rect number of bytes. If the master mistakenly sends more bytes than are required by the current command, the extra bytes are either ignored (if the MAXQ3180 is busy processing the previous command) or are inter- preted as the beginning of a new command. If the mas- ter sends fewer bytes than are required by the current command, the MAXQ3180 waits for approximately 200ms, then drops the transaction and resets the com- munication channel. The duration of the timeout can be configured through the COM_TIMO register. Figures 6 and 7 show typical 2-byte reading and writing transfers (without CRC byte). CS SCLK MOSI MISO READING DATA FROM MAXQ3180 THROUGH SPI INTERFACE 00 01 ADDRESS DUMMY DUMMY DUMMY DUMMY 0xC1 0xC2 NACK (0x4E) DATA LSB DATA MSB ACK (0x41) Figure 6. Read SPI Transfer CS SCLK MOSI MISO 10 01 ADDRESS DUMMY DUMMY 0xC1 0xC2 ACK (0x41) NACK (0x4E) ACK (0x41) ACK (0x41) WRITING DATA TO MAXQ3180 THROUGH SPI INTERFACE DATA LSB DATA MSB Figure 7. Write SPI Transfer |
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