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MAXQ3180-RAN+ Datasheet(PDF) 24 Page - Maxim Integrated Products |
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MAXQ3180-RAN+ Datasheet(HTML) 24 Page - Maxim Integrated Products |
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24 / 48 page ![]() Low-Power, Multifunction, Polyphase AFE 24 ______________________________________________________________________________________ Table 4. RAM Register Summary (continued) NAME ADDRESS (BYTE) DESCRIPTION R/W DEFAULT VALUE (HEX) BITS NAME DESCRIPTION REV_TIMO 124 0x07C Reverse Pulse Direction Timeout R/W 0x000B 15:0 Number of line cycles to detect reverse pulse direction ACC_TIMO 126 0x07E Energy Accumulation Delay Timeout R/W 0x0032 15:0 Number of line cycles before starting energy accumulation COM_TIMO 128 0x080 Communication Timeout R/W 0x03E8 15:0 Number of frames to reset communication channel 15:8 — These bits are reserved and should be set to 0 7 ADCASD Automatic shutdown disable 6 ADCRY Sample ready (system) 5:4 ADCCD [1:0] ADC clock divider 00: ADC = SYSCLK 01: ADC = SYSCLK/2 10: ADC = SYSCLK/4 11: Reserved 3 ADCBY ADC busy (system) 2 ADCIE ADC interrupt enable (system) 1 ARBE Internal VREF enable R_ACFG 130 0x082 Analog Control Shadow R/W 0x0007 0 ADCE ADC enable 15:9 — Reserved. Should be set to 0. R_ADCRATE 132 0x084 Analog Control Shadow R/W 0x00C7 8:0 R_ADCRATE [8:0] Number of SYSCLKs between two consecutive ADC conversions minus 1 15:7 — Reserved. Should be set to 0. R_ADCACQ 134 0x086 Analog Control Shadow R/W 0x002F 6:0 R_ADCACQ [6:0] Number of SYSCLKs for amplifier to acquire input signal before conversion minus 1 15:8, 5:3 — Reserved. Should be set to 0. 7 ESPII SPI interrupt enable (system) 6 SAS SSEL active level select 0: SSEL active low 1: SSEL active high 5:3 — These bits are reserved and should be set to 0 2 CHR SPI character length bit 0: 8 bits 1: 16 bits 1 CKPHA SPI clock phase select R_SPICF 136 0x088 SPI Control Shadow R/W 0x0080 0 CKPOL SPI clock polarity select |
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