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AM2431BSDGHIALVR. Datasheet(PDF) 148 Page - Texas Instruments |
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AM2431BSDGHIALVR. Datasheet(HTML) 148 Page - Texas Instruments |
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148 / 282 page ![]() 6.11.5.1.3 CPSW3G RGMII Timing Table 6-32, Table 6-33, Table 6-34, Figure 6-26, Table 6-35, Table 6-36, and Figure 6-27 present timing conditions, timing requirements, and switching characteristics for CPSW3G RGMII. Table 6-32. CPSW3G RGMII Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate VDD(1) = 1.8V 1.44 5 V/ns VDD(1) = 3.3V 2.64 5 OUTPUT CONDITIONS CL Output load capacitance 2 20 pF PCB CONNECTIVITY REQUIREMENTS td(Trace Mismatch Delay) Propagation delay mismatch across all traces RGMII[x]_RXC, RGMII[x]_RD[3:0], RGMII[x]_RX_CTL 50 ps RGMII[x]_TXC, RGMII[x]_TD[3:0], RGMII[x]_TX_CTL 50 ps (1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see POWER column of the Pin Attributes table. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com 148 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated Product Folder Links: AM2434 AM2432 AM2431 |
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