AM2431BSDGHIALVR. datasheet(144/282 Pages) TI2

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6.11.5 Peripherals

6.11.5.1 CPSW3G

For more details about features and additional description information on the device Gigabit Ethernet MAC, see

the corresponding subsections within Signal Descriptions and Detailed Description sections.

Note

CPSW3G MDIO0, CPSW3G RMII1, CPSW3G RMII2, and CPSW3G RGMII1 have one or more

signals which can be multiplexed to more than one pin. Timing requirements and switching

characteristics defined in this section are only valid for specific pin combinations known as IOSETs.

Valid pin combinations or IOSETs for these interfaces can be found in the tables of the CPSW3G

IOSETs section.

6.11.5.1.1 CPSW3G MDIO Timing

Table 6-25, Table 6-26, Table 6-27, and Figure 6-22 present timing conditions, timing requirements, and

switching characteristics for CPSW3G MDIO.

Table 6-25. CPSW3G MDIO Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

0.9

3.6

V/ns

OUTPUT CONDITIONS

Output load capacitance

470

PCB CONNECTIVITY REQUIREMENTS

td(Trace Delay)

Propagation delay of each trace

td(Trace Mismatch Delay)

Propagation delay mismatch across all traces

Table 6-26. CPSW3G MDIO Timing Requirements

see Figure 6-22

NO.

PARAMETER

MIN

MAX

UNIT

MDIO1 tsu(MDIO_MDC)

Setup time, MDIO[x]_MDIO valid before MDIO[x]_MDC high

MDIO2 th(MDC_MDIO)

Hold time, MDIO[x]_MDIO valid after MDIO[x]_MDC high

Table 6-27. CPWS3G MDIO Switching Characteristics

see Figure 6-22

NO.

PARAMETER

MIN

MAX

UNIT

MDIO3 tc(MDC)

Cycle time, MDIO[x]_MDC

400

MDIO4 tw(MDCH)

Pulse Duration, MDIO[x]_MDC high

160

MDIO5 tw(MDCL)

Pulse Duration, MDIO[x]_MDC low

160

MDIO7 td(MDC_MDIO)

Delay time, MDIO[x]_MDC low to MDIO[x]_MDIO valid

-10

AM2434, AM2432, AM2431

SPRSP65J – APRIL 2021 – REVISED JUNE 2026

www.ti.com

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