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AM2431BSDGHIALVR. Datasheet(PDF) 152 Page - Texas Instruments |
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AM2431BSDGHIALVR. Datasheet(HTML) 152 Page - Texas Instruments |
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152 / 282 page ![]() 6.11.5.2 DDRSS For more details about features and additional description information on the device (LP)DDR4 Memory Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections. Table 6-40 and Figure 6-28 present switching characteristics for DDRSS. Table 6-40. DDRSS Switching Characteristics see Figure 6-28 NO. PARAMETER DDR TYPE MIN MAX UNIT 1 tc(DDR_CKP/ DDR_CKN) Cycle time, DDR_CKP and DDR_CKN LPDDR4 1.25(1) 20 ns DDR4 1.25(1) 1.6 ns (1) Minimum DDR clock Cycle time will be limited based on the specific memory type (vendor) used in a system and by PCB implementation. Refer to AM64x\AM243x DDR Board Design and Layout Guidelines for the proper PCB implementation to achieve maximum DDR frequency. DDR0_CKP 1 DDR0_CKN Figure 6-28. DDRSS Switching Characteristics For more information, see DDR Subsystem (DDRSS) section in Memory Controllers chapter in the device TRM. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com 152 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated Product Folder Links: AM2434 AM2432 AM2431 |
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