AM2431BSDGHIALVR. datasheet(164/282 Pages) TI2

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–

H = 0.5 × OEExtraDelay × GPMC0_FCLK(14) if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and

OEOffTime are even)

–

H = (1 + 0.5 × OEExtraDelay) × GPMC0_FCLK(14) otherwise

•

Case GPMCFCLKDIVIDER = 2:

–

H = 0.5 × OEExtraDelay × GPMC0_FCLK(14) if ((OEOffTime - ClkActivationTime) is a multiple of 3)

–

H = (1 + 0.5 × OEExtraDelay) × GPMC0_FCLK(14) if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3)

–

H = (2 + 0.5 × OEExtraDelay) × GPMC0_FCLK(14) if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3)

(9)

For WE falling edge (WE activated):

•

Case GPMCFCLKDIVIDER = 0:

–

I = 0.5 × WEExtraDelay × GPMC0_FCLK(14)

•

Case GPMCFCLKDIVIDER = 1:

–

I = 0.5 × WEExtraDelay × GPMC0_FCLK(14) if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and

WEOnTime are even)

–

I = (1 + 0.5 × WEExtraDelay) × GPMC0_FCLK(14) otherwise

•

Case GPMCFCLKDIVIDER = 2:

–

I = 0.5 × WEExtraDelay × GPMC0_FCLK(14) if ((WEOnTime - ClkActivationTime) is a multiple of 3)

–

I = (1 + 0.5 × WEExtraDelay) × GPMC0_FCLK(14) if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3)

–

I = (2 + 0.5 × WEExtraDelay) × GPMC0_FCLK(14) if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3)

For WE rising edge (WE deactivated):

•

Case GPMCFCLKDIVIDER = 0:

–

I = 0.5 × WEExtraDelay × GPMC0_FCLK (14)

•

Case GPMCFCLKDIVIDER = 1:

–

I = 0.5 × WEExtraDelay × GPMC0_FCLK(14) if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and

WEOffTime are even)

–

I = (1 + 0.5 × WEExtraDelay) × GPMC0_FCLK(14) otherwise

•

Case GPMCFCLKDIVIDER = 2:

–

I = 0.5 × WEExtraDelay × GPMC0_FCLK(14) if ((WEOffTime - ClkActivationTime) is a multiple of 3)

–

I = (1 + 0.5 × WEExtraDelay) × GPMC0_FCLK(14) if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3)

–

I = (2 + 0.5 × WEExtraDelay) × GPMC0_FCLK(14) if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3)

(10) Case GPMC0_CLK in div_by_1_mode(17), first transfer only: Data and byte enables transition on rise edge of GPMC0_CLK

•

Non-multiplexed mode: data transition at start of cycle

•

Multiplexed mode: data transition at WRDATAONADMUXBUS × (TimeParaGranularity + 1) × GPMC0_FCLK(14)

(11) Case GPMC0_CLK in div_by_1_mode(17), all data and byte enables after initial transfer: Data and byte enables transition on fall edge

of GPMC0_CLK (Half cycle of GPMC0_CLK)

(12) Case GPMC0_CLK in not_div_by_1_mode(17) (GPMC0_CLK divided down from GPMC0_FCLK): All data and byte enables

transition on fall edge of GPMC0_CLK (Half cycle of GPMC0_CLK). ClkActivationTime, GPMCFCLKDIVIDER, RDACCESSTIME/

WRACCESSTIME, and PAGEBURSTACCESSTIME configuration must be configured to enforce data and byte enables transition on

falling edge of GPMC0_CLK (to be latched on rise edge of GPMC0_CLK)

(13) In GPMC0_CSn[i], i is equal to 0, 1, 2 or 3.

(14) P = GPMC0_CLK period in ns

(15) For read: K = (ADVRdOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC0_FCLK(14)

For write: K = (ADVWrOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC0_FCLK(14)

(16) Related to the GPMC0_CLK output clock maximum and minimum frequencies programmable in the GPMC module by setting the

GPMC0_CONFIG1_i configuration register bit field GPMCFCLKDIVIDER.

(17) For div_by_1_mode:

•

GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:

–

GPMC0_CLK frequency = GPMC0_FCLK frequency

For not_div_by_1_mode:

•

GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 1h to 3h:

–

GPMC0_CLK frequency = GPMC0_FCLK frequency / (2 to 4)

AM2434, AM2432, AM2431

SPRSP65J – APRIL 2021 – REVISED JUNE 2026

www.ti.com

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