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AM2431BSDGHIALVR. Datasheet(PDF) 161 Page - Texas Instruments

Part # AM2431BSDGHIALVR.
Description  AM243x Sitara™ Microcontrollers
PDF  282 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

AM2431BSDGHIALVR. Datasheet(HTML) 161 Page - Texas Instruments

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(4)
For div_by_1_mode:
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
–
GPMC0_CLK frequency = GPMC0_FCLK frequency
For not_div_by_1_mode:
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 1h to 3h:
–
GPMC0_CLK frequency = GPMC0_FCLK frequency / (2 to 4)
Table 6-59. GPMC and NOR Flash Switching Characteristics – Synchronous Mode
see Figure 6-39, Figure 6-40, Figure 6-41, Figure 6-42, and Figure 6-43
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
F0
tc(clk)
Cycle time, GPMC0_CLK(16)
7.52(1)
ns
F1
tw(clkH)
Typical pulse duration, GPMC0_CLK high
0.475P(14) -
0.3
ns
F1
tw(clkL)
Typical pulse duration, GPMC0_CLK low
0.475P(14) -
0.3
ns
F2
td(clkH-csn[i]V)
Delay time, GPMC0_CLK rising edge to GPMC0_CSn[i](13)
transition
F(6) - 2.2
F(6) + 1.31
ns
F3
td(clkH-csn[i]IV)
Delay time, GPMC0_CLK rising edge to GPMC0_CSn[i](13)
invalid
D(5) - 2.2
D(5) + 1.31
ns
F4
td(aV-clk)
Delay time, GPMC0_A[27:1] valid to GPMC0_CLK first edge
B(3) - 2.3
B(3) + 4.5
ns
F5
td(clkH-aIV)
Delay time, GPMC0_CLK rising edge to GPMC0_A[27:1]
invalid
-2.3
4.5
ns
F6
td(be[x]nV-clk)
Delay time, GPMC0_BE0n_CLE, GPMC0_BE1n,
GPMC0_BE2n, GPMC0_BE3n valid to GPMC0_CLK first edge
B(3) - 2.3
B(3) + 1.9
ns
F7
td(clkH-be[x]nIV)
Delay time, GPMC0_CLK rising edge to GPMC0_BE0n_CLE,
GPMC0_BE1n, GPMC0_BE2n, GPMC0_BE3n invalid
D(5) - 2.3
D(5) + 1.9
ns
F8
td(clkH-advn)
Delay time, GPMC0_CLK rising edge to GPMC0_ADVn_ALE
transition
G(7) - 2.3
G(7) + 4.5
ns
F9
td(clkH-advnIV)
Delay time, GPMC0_CLK rising edge to GPMC0_ADVn_ALE
invalid
D(5) - 2.3
D(5) + 4.5
ns
F10
td(clkH-oen)
Delay time, GPMC0_CLK rising edge to GPMC0_OEn_REn
transition
H(8) - 2.3
H(8) + 3.5
ns
F11
td(clkH-oenIV)
Delay time, GPMC0_CLK rising edge to GPMC0_OEn_REn
invalid
D(5) - 2.3
D(5) + 3.5
ns
F14
td(clkH-wen)
Delay time, GPMC0_CLK rising edge to GPMC0_WEn
transition
I(9) - 2.3
I(9) + 4.5
ns
F15
td(clkH-do)
Delay time, GPMC0_CLK rising edge to GPMC0_AD[n:0](1)
transition(10)
-2.3
2.7
ns
F15
td(clkL-do)
Delay time, GPMC0_CLK falling edge to GPMC0_AD[n:0](1)
transition(11)
-2.3
2.7
ns
F15
td(clkL-do)
Delay time, GPMC0_CLK falling edge to GPMC0_AD[n:0](1)
transition(12)
-2.3
2.7
ns
F17
td(clkH-be[x]n)
Delay time, GPMC0_CLK rising edge to GPMC0_BE0n_CLE,
GPMC0_BE1n, GPMC0_BE2n, GPMC0_BE3n transition(10)
-2.3
1.9
ns
F17
td(clkL-be[x]n)
Delay time, GPMC0_CLK falling edge to GPMC0_BE0n_CLE,
GPMC0_BE1n, GPMC0_BE2n, GPMC0_BE3n transition(11)
-2.3
1.9
ns
F17
td(clkL-be[x]n)
Delay time, GPMC0_CLK falling edge to GPMC0_BE0n_CLE,
GPMC0_BE1n, GPMC0_BE2n, GPMC0_BE3n transition(12)
-2.3
1.9
ns
F18
tw(csnV)
Pulse duration, GPMC0_CSn[i](13) low
A(2)
ns
F19
tw(be[x]nV)
Pulse duration, GPMC0_BE0n_CLE, GPMC0_BE1n,
GPMC0_BE2n, GPMC0_BE3n low
C(4)
ns
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AM2434, AM2432, AM2431
SPRSP65J – APRIL 2021 – REVISED JUNE 2026
Copyright © 2026 Texas Instruments Incorporated
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Product Folder Links: AM2434 AM2432 AM2431



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