AM2431BSDGHIALVR. datasheet(157/282 Pages) TI2

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6.11.5.6 FSI

Table 6-50, Table 6-51, Figure 6-36, Table 6-52, Figure 6-37, Table 6-53, and Figure 6-38 present timing

conditions, timing requirements, and switching characteristics for FSI.

Table 6-50. FSI Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

0.8

V/ns

OUTPUT CONDITIONS

Output load capacitance

Table 6-51. FSI Timing Requirements

see Figure 6-36

NO.

MIN

MAX

UNIT

FSIR1

tc(RX_CLK)

Cycle time, FSI_RXn_CLK

FSIR2

tw(RX_CLK)

Pulse width, FSI_RXn_CLK low or FSI_RXn_CLK high

0.5P - 1

(1) 0.5P + 1 (1)

FSIR3

tsu(RX_D-RX_CLK)

Setup time, FSI_RXn_D[1:0] valid before FSI_RXn_CLK

FSIR4

th(RX_CLK-RX_D)

Hold time, FSI_RXn_D[1:0] valid after FSI_RXn_CLK

2.5

(1)

P = FSI_RXn_CLK period in ns.

FSI_RXn_CLK

FSIR2

FSIR1

FSIR3

FSI_RXn_D0

FSI_RXn_D1

FSIR4

FSIR2

Figure 6-36. FSI Timing Requirements

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AM2434, AM2432, AM2431

SPRSP65J – APRIL 2021 – REVISED JUNE 2026

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