AM2431BSDGHIALVR. datasheet(160/282 Pages) TI2

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6.11.5.8 GPMC

For more details about features and additional description information on the device General-Purpose Memory

Controller, see the corresponding subsections within Signal Descriptions and Detailed Description sections.

Note

GPMC has one or more signals which can be multiplexed to more than one pin. Timing requirements

and switching characteristics defined in this section are only valid for specific pin combinations known

as IOSETs. Valid pin combinations or IOSETs for this interface is shown in Section 5.3.12.1.1.

Table 6-57 presents timing conditions for GPMC.

Table 6-57. GPMC Timing Conditions

PARAMETER

MIN

MAX UNIT

INPUT CONDITIONS

SRI

Input slew rate

1.65

V/ns

OUTPUT CONDITIONS

Output load capacitance

133MHz Synchronous Mode

All other modes

PCB CONNECTIVITY REQUIREMENTS

td(Trace Delay)

Propagation delay of each trace

133MHz Synchronous Mode

140

360

All other modes

140

720

td(Trace Mismatch

Delay)

Propagation delay mismatch across all traces

200

For more information, see General-Purpose Memory Controller (GPMC) section in Peripherals chapter in the

device TRM.

6.11.5.8.1 GPMC and NOR Flash — Synchronous Mode

Table 6-58 and Table 6-59 present timing requirements and switching characteristics for GPMC and NOR Flash -

Synchronous Mode.

Table 6-58. GPMC and NOR Flash Timing Requirements — Synchronous Mode

see Figure 6-39, Figure 6-40, and Figure 6-43

NO.

PARAMETER

DESCRIPTION

MODE(4)

MIN

MAX

MIN

MAX

UNIT

32-bit data bus

(up to 100MHz)

(1)

16-bit data bus

(up to 133MHz)

(1)

F12 tsu(dV-clkH)

Setup time, GPMC0_AD[n:0](1) valid

before GPMC0_CLK high

div_by_1_mode

1.81

1.12

not_div_by_1_mode

1.06

3.5

F13 th(clkH-dV)

Hold time, GPMC0_AD[n:0](1) valid

after GPMC0_CLK high

div_by_1_mode

2.29

not_div_by_1_mode

2.29

F21 tsu(waitV-clkH)

Setup time, GPMC0_WAIT[j](2) (3)

valid before GPMC0_CLK high

div_by_1_mode

1.81

1.12

not_div_by_1_mode

1.06

3.5

F22 th(clkH-waitV)

Hold time, GPMC0_WAIT[j](2) (3)

valid after GPMC0_CLK high

div_by_1_mode

2.29

not_div_by_1_mode

2.29

(1)

Synchronous Mode supports a 32-bit data bus (GPMC0_AD[31:0]) with GPMC0_CLK up to 100MHz and a 16-bit data bus

(GPMC0_AD[15:0]) with GPMC0_CLK up to 133MHz. Select the clock source of GPMC0_FCLK which feeds GPMC0_CLK by writing

to the CTRLMMR_GPMC0_CLKSEL register:

•

133MHz: CLK_SEL = 0h - MAIN_PLL0_HSDIV3_CLKOUT (default)

•

100MHz: CLK_SEL = 1h - MAIN_PLL2_HSDIV3_CLKOUT

(2)

In GPMC_WAIT[j], j is equal to 0 or 1.

(3)

Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of wait monitoring feature, see General-

Purpose Memory Controller (GPMC) section in the device TRM.

AM2434, AM2432, AM2431

SPRSP65J – APRIL 2021 – REVISED JUNE 2026

www.ti.com

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