AM2431BSDGHIALVR. datasheet(226/282 Pages) TI2

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6.11.5.16.4 PRU_ICSSG Universal Asynchronous Receiver Transmitter (UART)

Table 6-127. PRU_ICSSG UART Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

0.5

V/ns

OUTPUT CONDITIONS

Output load capacitance

30(1)

(1)

This value represents an absolute maximum load capacitance. As the UART baud rate increases, it may be necessary to reduce the

load capacitance to a value less than this maximum limit to provide enough timing margin for the attached device. The output rise/fall

times increase as capacitive load increases, which decreases the time data is valid for the receiver of the attached devices. Therefore,

it is important to understand the minimum data valid time required by the attached device at the operating baud rate. Then use the

device IBIS models to verify the actual load capacitance on the UART signals does not increase the rise/fall times beyond the point

where the minimum data valid time of the attached device is violated.

6.11.5.16.4.1 PRU_ICSSG UART Timing

Table 6-128. PRU_ICSSG UART Timing Requirements

see Figure 6-103

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

tw(RXD)

Pulse width, receive data bit high or low

0.95U(1)

(2)

1.05U(1)

(2)

tw(RXDS)

Pulse width, receive start bit low

0.95U(1)

(2)

(1)

U = UART baud time in ns = 1/programmed baud rate.

(2)

This value defines the data valid time, where the input voltage is required to be above VIH or below VIL.

Table 6-129. PRU_ICSSG UART Switching Characteristics

see Figure 6-103

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

f(baud)

Programmed baud rate

Mbps

tw(TXD)

Pulse width, transmit data bit high or low

U(1) - 2

U(1) + 2

tw(TXDS)

Pulse width, transmit start bit low

U(1) - 2

U(1) + 2

(1)

U = UART baud time in ns = 1/actual baud rate, where the actual baud rate is defined in the UART Baud Rate Settings table of the

device TRM.

Start

Bit

Data Bits

PRG _UART0_TXD

PRU_UART_TIMING_01_RCVRVIHVIL

Data Bits

Bit

Start

PRG _UART0_RXD

Figure 6-103. PRU_ICSSG UART Timing Requirements and Switching Characteristics

AM2434, AM2432, AM2431

SPRSP65J – APRIL 2021 – REVISED JUNE 2026

www.ti.com

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