AM2431BSDGHIALVR. datasheet(229/282 Pages) TI2

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6.11.5.16.6.2 PRU_ICSSG MII Timing

Note

In order to ensure the MII_G_RT I/O timing values published in the device data sheet, the

PRU_ICSSG ICSSGn_CORE_CLK (where n = 0 to 1) core clock must be configured for 200MHz,

225MHz, or 250MHz and the TX_CLK_DELAYn (where n = 0 or 1) bit field in the ICSSG_TXCFG0/1

Table 6-136, Table 6-137, Figure 6-107, Table 6-138, Figure 6-108, Table 6-139, Figure 6-109, Table 6-140, and

Figure 6-110 present timing conditions, timing requirements, and switching characteristics for PRU_ICSSG MII.

Table 6-136. PRU_ICSSG MII Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

0.9

3.6

V/ns

OUTPUT CONDITIONS

Output load capacitance

Table 6-137. PRU_ICSSG MII Timing Requirements – MII[x]_RX_CLK

see Figure 6-107

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

PMIR1 tc(RX_CLK)

Cycle time, MII[x]_RX_CLK

10Mbps

399.96

400.04

100Mbps

39.996

40.004

PMIR2 tw(RX_CLKH)

Pulse Duration, MII[x]_RX_CLK High

10Mbps

140

260

100Mbps

PMIR3 tw(RX_CLKL)

Pulse Duration, MII[x]_RX_CLK Low

10Mbps

140

260

100Mbps

MII_RX_CLK

PMIR2

PMIR3

PMIR1

PRU_MII_RT_TIMING_04

Figure 6-107. PRU_ICSSG MII[x]_RX_CLK Timing

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AM2434, AM2432, AM2431

SPRSP65J – APRIL 2021 – REVISED JUNE 2026

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