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AM2431BSDGHIALVR. Datasheet(PDF) 230 Page - Texas Instruments |
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AM2431BSDGHIALVR. Datasheet(HTML) 230 Page - Texas Instruments |
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230 / 282 page  Table 6-138. PRU_ICSSG MII Timing Requirements – MII[x]_RXD[3:0], MII[x]_RX_DV, and MII[x]_RX_ER see Figure 6-108 NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PMIR4 tsu(RXD-RX_CLK) Setup time, MII[x]_RXD[3:0] valid before MII[x]_RX_CLK 10Mbps 8 ns tsu(RX_DV-RX_CLK) Setup time, MII[x]_RX_DV valid before MII[x]_RX_CLK 8 ns tsu(RX_ER-RX_CLK) Setup time, MII[x]_RX_ER valid before MII[x]_RX_CLK 8 ns tsu(RXD-RX_CLK) Setup time, MII[x]_RXD[3:0] valid before MII[x]_RX_CLK 100Mbps 8 ns tsu(RX_DV-RX_CLK) Setup time, MII[x]_RX_DV valid before MII[x]_RX_CLK 8 ns tsu(RX_ER-RX_CLK) Setup time, MII[x]_RX_ER valid before MII[x]_RX_CLK 8 ns PMIR5 th(RX_CLK-RXD) Hold time, MII[x]_RXD[3:0] valid after MII[x]_ RX_CLK 10Mbps 8 ns th(RX_CLK-RX_DV) Hold time, MII[x]_RX_DV valid after MII[x]_RX_CLK 8 ns th(RX_CLK-RX_ER) Hold time, MII[x]_RX_ER valid after MII[x]_RX_CLK 8 ns th(RX_CLK-RXD) Hold time, MII[x]_RXD[3:0] valid after MII[x]_ RX_CLK 100Mbps 8 ns th(RX_CLK-RX_DV) Hold time, MII[x]_RX_DV valid after MII[x]_RX_CLK 8 ns th(RX_CLK-RX_ER) Hold time, MII[x]_RX_ER valid after MII[x]_RX_CLK 8 ns MII_RX_CLK PMIR4 PMIR5 MII_RXD[3:0], MII_RX_DV, MII_RX_ER Figure 6-108. PRU_ICSSG MII[x]_RXD[3:0], MII[x]_RX_DV, and MII[x]_RX_ER Timing Table 6-139. PRU_ICSSG MII Timing Requirements – MII[x]_TX_CLK see Figure 6-109 NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PMIT1 tc(TX_CLK) Cycle time, MII[x]_TX_CLK 10Mbps 399.96 400.04 ns 100Mbps 39.996 40.004 ns PMIT2 tw(TX_CLKH) Pulse Duration, MII[x]_TX_CLK High 10Mbps 140 260 ns 100Mbps 14 26 ns PMIT3 tw(TX_CLKL) Pulse Duration, MII[x]_TX_CLK Low 10Mbps 140 260 ns 100Mbps 14 26 ns MII_TX_CLK PMIT2 PMIT3 PMIT1 Figure 6-109. PRU_ICSSG MII[x]_TX_CLK Timing AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com 230 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated Product Folder Links: AM2434 AM2432 AM2431 |
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