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R5F564MFDDFB Datasheet(PDF) 85 Page - Renesas Technology Corp |
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R5F564MFDDFB Datasheet(HTML) 85 Page - Renesas Technology Corp |
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85 / 162 page  R01DS0173EJ0120 Rev.1.20 Page 85 of 162 Oct 20, 2022 RX64M Group 2. Electrical Characteristics 2.3.5 Bus Timing Table 2.23 Bus Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0, VCC_USBA = AVCC_USBA = 3.0 to 3.6 V, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V, ICLK = PCLKA = 8 to 120 MHz, PCLKB = BCLK = SDCLK = 8 to 60 MHz, Ta = Topr Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF High-drive output is selected by the driving ability control register. Item Symbol Min. Max. Unit Test Conditions Address delay time tAD — 12.5 ns Figure 2.16 to Figure 2.21 Byte control delay time tBCD — 12.5 ns CS# delay time tCSD — 12.5 ns ALE delay time tALED — 12.5 ns RD# delay time tRSD — 12.5 ns Read data setup time tRDS 12.5 — ns Read data hold time tRDH 0— ns WR# delay time tWRD — 12.5 ns Write data delay time tWDD — 12.5 ns Write data hold time tWDH 0— ns WAIT# setup time tWTS 12.5 — ns Figure 2.22 WAIT# hold time tWTH 0— ns Address delay time 2 (SDRAM) tAD2 1 12.5 ns Figure 2.23 CS# delay time 2 (SDRAM) tCSD2 1 12.5 ns DQM delay time (SDRAM) tDQMD 1 12.5 ns CKE delay time (SDRAM) tCKED 1 12.5 ns Read data setup time 2 (SDRAM) tRDS2 10 — ns Read data hold time 2 (SDRAM) tRDH2 0— ns Write data delay time 2 (SDRAM) tWDD2 — 12.5 ns Write data hold time 2 (SDRAM) tWDH2 1— ns WE# delay time (SDRAM) tWED 1 12.5 ns RAS# delay time (SDRAM) tRASD 1 12.5 ns CAS# delay time (SDRAM) tCASD 1 12.5 ns |
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