RZSLASHG2H datasheet(117/169 Pages) RENESAS

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RZ/G Series, 2nd Generation Datasheet

Section 3. Electrical Characteristics

R01DS0483EJ0101 Rev.1.01

Page 117 of 169

Jun 30, 2025

3.23 MSIOF

Table 3.23.1 MSIOF Module Signal Timing

Conditions: VDDQ33 = 3.3 V ± 0.2 V [RZ/G2H, RZ/G2M V1.3,RZ/G2M V3.0, RZ/G2N],

VDDQ33 = 3.3 V ± 0.3 V [RZ/G2E],

GND = VSS = 0 V, Tc = −40 to +115 °C [RZ/G2H, RZ/G2M V1.3],

Ta = -40 to +85 °C [RZ/G2M V3.0, RZ/G2N, RZ/G2E],

Tj = -40 to +115 °C [RZ/G2M V3.0, RZ/G2N, RZ/G2E], CL = 30 pF

Item

Symbol

Min.

Max.

Unit

Figures

MSIOF_SCK clock cycle time

(when master TX or slave RX)

tMSCYC

4 × tpcyc*

—

Figure 3.23.1,

Figure 3.23.4

MSIOF_SCK clock cycle time

(when master RX or slave TX)

tMSCYC

8 × tpcyc*

—

MSIOF_SCK output clock high-level width

tMSWHO

0.4 × tMSCYC

—

MSIOF_SCK output clock low-level width

tMSWLO

0.4 × tMSCYC

—

MSIOF_SCK input high-level width

tMSWHI

0.4 × tMSCYC

—

MSIOF_SCK input low-level width

tMSWLI

0.4 × tMSCYC

—

MSIOF_SYNC input setup time in slave mode

tTSFSS

—

MSIOF_SYNC input hold time in slave mode

tTSFSH

—

MSIOF_TXD output delay time1 in slave mode

tTSDD1

MSIOF_TXD output delay time2 in slave mode

tTSDD2

MSIOF_RXD input setup time in slave mode

tTSRDS

—

MSIOF_RXD input hold time in slave mode

tTSRDH

—

MSIOF_SYNC output delay time in master mode

tTMSFD

-2

MSIOF_TXD output delay time in master mode

tTMDD

-2

MSIOF_RXD input setup time in master mode

tTMRDS

—

MSIOF_RXD input hold time in master mode

tTMRDH

—

Note:

tpcyc is a cycle time of peripheral clock (MSOϕ).

RZ/G2H

RZ/G2M V1.3

RZ/G2N

RZ/G2E

RZ/G2M V3.0

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