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RZ/G2H Datasheet(PDF) 121 Page - Renesas Technology Corp

Part # RZ/G2H
Description  RZ/G Series, 2nd Generation
PDF  169 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

RZ/G2H Datasheet(HTML) 121 Page - Renesas Technology Corp

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RZ/G Series, 2nd Generation Datasheet
Section 3. Electrical Characteristics
R01DS0483EJ0101 Rev.1.01
Page 121 of 169
Jun 30, 2025
Table 3.24.2 RPC Timing [RZ/G2E]
Conditions:
VDDQ_QSPI = 1.8V ± 0.1 V, GND = VSS = 0 V,
Ta = −40 to + 85 °C,
Tj = −40 to + 115 °C,
CL = 15 pF
Item
Symbol
Min.
Typ.
Max.
Unit
Figures
SPCLK clock cycle time
(HyperFlash)
tSPCYC
6.66
—
—
ns
Figure 3.24.1
SPCLK clock cycle time
(QSPI Flash)
12.50
—
—
ns
SPCLK high pulse width
tSPWH
0.45
—
0.55
tSPCYC
SPCLK low pulse width
tSPWL
0.45
—
0.55
tSPCYC
SPCLK rise time
tSPR
—
—
2.0
ns
SPCLK fall time
tSPF
—
—
2.0
ns
SPCLK skew
tSPSKEW —
—
0.04
tSPCYC
SSL to setup time
tLEAD
1 × tSPCYC – 3
—
8 × tSPCYC + 3
ns
Figure 3.24.2,
Figure 3.24.3,
Figure 3.24.4
SSL to hold time
tLAG
5.5 × tSPCYC – 3 —
8.5 × tSPCYC + 3 ns
Data input valid setup time SDR tVSS
—
—
0.5 × tSPCYC + 3 ns
Figure 3.24.2
Data input valid hold time SDR
tVHS
0
—
—
ns
Data output setup time
tOS
0.5 × tSPCYC – 2 —
—
ns
Data output hold time
tOH
0.5 × tSPCYC – 2 —
—
ns
Data input valid setup time DDR tVSD
—
—
6.5
ns
Figure 3.24.3
Data input valid hold time DDR
tVHD
0.32 × tSPCYC
—
—
ns
Data to Data Strobe Skew
tDDSS
-0.65
—
0.65
ns
Figure 3.24.4
SPCLK to Data Strobe Skew
tCDSS
—
—
7.0
ns
Output Data Setup time in DDR
mode
tSDDR
0.25 × tSPCYC –
0.6
—
0.25 × tSPCYC +
0.6
ns
Figure 3.24.3,
Figure 3.24.4
Output Data Hold time in DDR
mode
tHDDR
0.25 × tSPCYC –
0.6
—
0.25 × tSPCYC +
0.6
ns
Input Slew rate with Data Strobe
usage
tDSISR
0.94
—
—
V/ns
Figure 3.24.5
RPC_RESET assert time
tRPCRA
0
—
—
ns
Figure 3.24.6
RPC_RESET negate time
tRPCRN
10
—
—
ns
Figure 3.24.6



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