RZSLASHG2UL datasheet(29/67 Pages) RENESAS

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RZ/G2UL Group

3. Electrical Characteristics

R01DS0486EJ0110 Rev.1.10

Page 29 of 67

Jun 16, 2025

3.5.2

SDHI Access Timing

3.5.2.1

SDHI Access Timing (SDR 3.3-V)

Table 3.21

SDHC AC Access Timing (SDR at 3.3-V Operation)

Default Speed Mode

(16.67 MHz)

High Speed Mode

(33.33 MHz)

Item

Symbol

Min.

Max.

Min.

Max.

Unit

Figures

SD_CLK clock cycle

tSDCYC

60.00

—

30.0

—

Figure 3.8

SD_CLK clock high level width

tSDWH

23.50

—

13.50

—

SD_CLK clock low level width

tSDWL

23.50

—

13.50

—

SD_CLK clock rise time

tSDLH

—

SD_CLK clock fall time

tSDHL

—

SD_CMD,SD_DATA output delay

tSDODLY

−4.50

4.0

−4.50

4.0

SD_CMD,SD_DATA input set up time

tSDIS

5.5

—

5.5

—

SD_CMD,SD_DATA input hold time

tSDIH

2.0

—

2.0

—

SD_CMD,SD_DATA input data width

tSDIDW

—

SD_CLK

(output)

SD_CMD/SD_DATA

(input)

tSDCYC

tSDWL

tSDWH

tSDLH

tSDHL

tSDIS tSDIH

tSDIDW

tSDODLY(max)

tSDODLY(min)

SD_CMD/SD_DATA

(output)

Figure 3.8

SDHC Interface Timing (SDR 3.3-V Power Supply)

NOTE

The disclosure of other characteristics of the SD interface needs the conclusion of the following agreement.

● SD Host/Ancillary Product License Agreement (SD HALA)

For details, contact your local sales representatives.

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