RZSLASHG2UL datasheet(53/67 Pages) RENESAS

53 / 67 page

RZ/G2UL Group

3. Electrical Characteristics

R01DS0486EJ0110 Rev.1.10

Page 53 of 67

Jun 16, 2025

3.5.14

I2C Bus Interface Access Timing

Table 3.41

I2C Bus Interface Timing

Standard Mode (Sm)

Fast Mode (Fm)

Fast Mode Plus (Fm+)

Item

Symbol

I/O

Min.

Max.

Min.

Max.

Min.

Max.

Unit

SCL clock frequency

fCLK

I/O

100

400

1000

kHz

Bus free time (between

stop and start condition)

tBUF

I/O

4.7

—

1.3

—

0.5

—

μs

Hold time*1

tHD:STA

I/O

4.0

—

0.6

—

0.26

—

μs

Low period of SCL clock

tLOW

I/O

4.7

—

1.3

—

0.5

—

μs

High period of SCL clock

tHIGH

I/O

4.0

—

0.6

—

0.26

—

μs

Setup time for start /

restart condition

tSU:STA

I/O

4.7

—

0.6

—

0.26

—

μs

Data hold time (I2C bus

device)

tHD:DAT

I/O

0*2

—

0*2

—

μs

Data setup time

tSU:DAT

I/O

250

—

100*3

—

SDA and SCL signal rise

time

Input

—

1000

300

—

120

SDA and SCL signal fall

time*3

Input

—

300

20 × (PVDD/

5.5 V)

300

20 × (PVDD/

5.5 V)

120

Output —

300

20 × (PVDD/

5.5 V)*6

300*6

20 × (PVDD/

5.5 V)*7

120*7

Setup time for STOP

condition

tSU:STO

I/O

4.0

—

0.6

—

0.26

—

μs

Capacitive load for each

bus line

—

400*4

—

400*4

—

550*4

Pulse width of spikes that

must be suppressed by

the input filter

tSP

Input

—

50*5

Note: In the above table and subsequently, SCL and SDA refer to the RIICnSCL and RIICnSDA signals, respectively.

Note: AC access timing condition: drive ability 4mA, output load 400pF, slew rate = slow

Note 1.

The first clock pulse is generated on the SCL line after the start condition has been issued and the hold time has elapsed.

Note 2.

This module requires a minimum of 300 ns hold time internally for the SDA signal to handle the period over which the falling

edge of SCL has not reached a defined level (time until the CnSCL signal reaches VIL (max.) from VIH (min.)).

Note 3.

The fast-mode I2C bus device can be used in the standard mode I2C bus system. In this case, the minimum value of the data

setup time (tSU: DAT (min.) 250 [ns]) must be satisfied.

If the system does not extend the low period of SCL clock (tLOW), this condition is automatically satisfied. If the system extends

the low period of SCL clock (tLOW), transmit the subsequent data bit to the SDA line before the SCL line is released (tR (max.)

+ tSU: DAT (min.) = 1000 + 250 = 1250 [ns]: (standard mode I2C bus specification)).

Note 4.

Total capacitance of one bus line. The allowable maximum bus capacitance may differ from this specification, depending on

the actual operating voltage and frequency of an application. For techniques to cope with a large bus capacitance, see the I2C

bus specification provided by NXP Semiconductors.

Note 5.

Noise is removed by the analog and digital input filters. The level of noise reduction of the digital input filter is determined by

the period of internal reference clock (IICϕ) and the NF[1:0] bits in RIICnMR3. For details, refer to Section 26, I²C Bus

Interface, in the User's Manual: Hardware.

Note 6.

External pull-up resistor is required 1077Ω to 1770Ω when using RIIC ch2 or RIIC ch3.

Note 7.

External pull-up resistor is required 240Ω to 257Ω when using RIIC ch2 or RIIC ch3.

RZ/G2UL Datasheet(PDF) 53 Page - Renesas Technology Corp

RZ/G2UL Datasheet(HTML) 53 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

Datasheet Download

Link URL