RZSLASHG2UL datasheet(59/67 Pages) RENESAS

59 / 67 page

RZ/G2UL Group

3. Electrical Characteristics

R01DS0486EJ0110 Rev.1.10

Page 59 of 67

Jun 16, 2025

3.5.17

Renesas Serial Peripheral Interface (RSPI) Access Timing

Table 3.44

Renesas Serial Peripheral Interface Timing

Item

Symbol

Min.

Max.

Unit

Figure

RSPCK clock cycle

Master

tSPcyc

4096

tp1cyc*1

Figure 3.45

Slave

4096

RSPCK clock high pulse width

Master

tSPCKWH

0.4

—

tSPcyc*1

Slave

0.4

—

RSPCK clock low pulse width

Master

tSPCKWL

0.4

—

tSPcyc*1

Slave

0.4

—

Data input setup time

Master

tSU

—

Figure 3.46 to

Figure 3.49

Slave

—

tp1cyc*1

Data input hold time

Master

—

Slave

—

tp1cyc*1

SSL setup time

Master

tLEAD

1 × tSPcyc − 20

8 × tSPcyc

Slave

—

tp1cyc*1

SSL hold time

Master

tLAG

1 × tSPcyc

8 × tSPcyc + 20

Slave

—

tp1cyc*1

Data output delay time

Master

tOD

—

Slave

—

tp1cyc*1

Data output hold time

Master

tOH

—

Slave

—

tp1cyc*1

Continuous transmission delay time

Master

tTD

1 × tSPcyc + 2 × tcyc 8 × tSPcyc + 2 × tcyc ns

Slave

4 × tcyc

—

Slave access time

tSA

—

tp1cyc*1

Figure 3.48,

Figure 3.49

Slave out release time

tREL

—

tp1cyc*1

Note: AC access timing condition: drive ability 12mA, output load 30pF, slew rate = fast

Note 1.

tp1cyc indicates peripheral clock means RSPIn_CLKB (P0ϕ) (0 to 2).

RSPIn_CK

slave select input

tSPCKWH

RSPIn_CK

master select output

tSPCKWL

tSPcyc

VIL

VIH

VIL

tSPCKWH

tSPCKWL

tSPcyc

VOL

VOH

VOL

Note: n = 0 to 2

Figure 3.45

Clock Timing

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