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AT80SND1C-ROTIL Datasheet(PDF) 127 Page - ATMEL Corporation |
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AT80SND1C-ROTIL Datasheet(HTML) 127 Page - ATMEL Corporation |
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127 / 210 page ![]() 127 AT8xC51SND1C 4109E–8051–06/03 Table 115. MMSTA Register MMSTA (S:DEh Read Only) – MMC Control and Status Register Reset Value = 0000 0000b 7654 3210 - - CBUSY CRC16S DATFS CRC7S RESPFS CFLCK Bit Number Bit Mnemonic Description 7 - 6 - Reserved The value read from these bits is always 0. Do not set these bits. 5CBUSY Card Busy Flag Set by hardware when the card sends a busy state on the data line. Cleared by hardware when the card no more sends a busy state on the data line. 4 CRC16S CRC16 Status Bit Transmission mode Set by hardware when the token response reports a good CRC. Cleared by hardware when the token response reports a bad CRC. Reception mode Set by hardware when the CRC16 received in the data block is correct. Cleared by hardware when the CRC16 received in the data block is not correct. 3DATFS Data Format Status Bit Transmission mode Set by hardware when the format of the token response is correct. Cleared by hardware when the format of the token response is not correct. Reception mode Set by hardware when the format of the frame is correct. Cleared by hardware when the format of the frame is not correct. 2 CRC7S CRC7 Status Bit Set by hardware when the CRC7 computed in the response is correct. Cleared by hardware when the CRC7 computed in the response is not correct. This bit is not relevant when CRCDIS is set. 1 RESPFS Response Format Status Bit Set by hardware when the format of a response is correct. Cleared by hardware when the format of a response is not correct. 0CFLCK Command FIFO Lock Bit Set by hardware to signal user not to write in the transmit command FIFO: busy state. Cleared by hardware to signal user the transmit command FIFO is available: idle state. |
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