R5F211B2DSP datasheet(40/339 Pages) RENESAS

40 / 339 page

R8C/1A Group, R8C/1B Group

5. Programmable I/O Ports

Rev.1.30

Dec 08, 2006

Page 24 of 315

REJ09B0252-0130

Programmable I/O Ports

There are 13 programmable Input/Output ports (I/O ports) P1, P3_3 to P3_5, P3_7, and P4_5. 4_2 can be used as an

input-only port. Also, P4_6 and P4_7 can be used as input-only ports if the main clock oscillation circuit is not used.

Table 5.1 lists an Overview of Programmable I/O Ports.

NOTES:

1. In input mode, whether an internal pull-up resistor is connected or not can be selected by registers PUR0 and

PUR1.

2. These ports can be used as the LED drive port by setting the DRR register to 1 (high).

3. When the main clock oscillation circuit is not used, P4_6 and P4_7 can be used as input -only ports.

5.1

Functions of Programmable I/O Ports

The PDi_j (j=0 to 7) bit in the PDi (i=1, 3, and 4) register controls I/O of ports P1, P3_3 to P3_5, P3_7, and P4_5.

The Pi register consists of a port latch to hold output data and a circuit to read pin states. Figures 5.1 to 5.3 show the

Configurations of Programmable I/O Ports.

Table 5.2 lists the Functions of Programmable I/O Ports. Also, Figure 5.5 shows Registers PD1, PD3, and PD4.

Figure 5.6 shows Registers P1 and P3, Figure 5.9 shows Registers PUR0 and PUR1 and Figure 5.10 shows the

DRR Register.

NOTE:

1. Nothing is assigned to bits PD3_0 to PD3_2, PD3_6, PD4_0 to PD4_4, PD4_6, and PD4_7.

5.2

Effect on Peripheral Functions

Programmable I/O ports function as I/O ports for peripheral functions (Refer to Table 1.6 Pin Name Information

by Pin Number of PLSP0020JB-A, PRDP0020BA-A Packages). Table 5.3 lists the Settings of PDi_j Bit when

Functioning as I/O Ports for Peripheral Functions. Refer to the description of each function for information on how

to set peripheral functions.

5.3

Pins Other than Programmable I/O Ports

Figure 5.4 shows the Configuration of I/O Pins.

Table 5.1

Overview of Programmable I/O Ports

Ports

I/O

Type of Output

I/O Setting

Internal Pull-Up

Resistor

Drive Capacity

Selection

I/O

CMOS3 state

Set per bit

Set every 4 bits(1)

Set every bit(2) of

P1_0 to P1_3

P3_3, P4_5

I/O

CMOS3 state

Set per bit

Set every bit(1)

None

P3_4, P3_5, P3_7

I/O

CMOS3 state

Set per bit

Set every 3 bits(1)

None

P4_2, P4_6, P4_7(3)

(No output function)

None

Table 5.2

Functions of Programmable I/O Ports

Operation when

Accessing

Pi Register

Value of PDi_j Bit in PDi Register(1)

When PDi_j Bit is Set to 0 (Input Mode)

When PDi_j Bit is Set to 1 (Output Mode)

Reading

Read pin input level

Read the port latch

Writing

Write to the port latch

Write to the port latch. The value written to the

port latch is output from the pin.

Table 5.3

Settings of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions

I/O of Peripheral Functions

PDi_j Bit Settings for Shared Pin Functions

Input

Set this bit to 0 (input mode).

Output

This bit can be set to either 0 or 1 (output regardless of the port setting).

R5F211B2DSP Datasheet(PDF) 40 Page - Renesas Technology Corp

R5F211B2DSP Datasheet(HTML) 40 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL