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R5F211B2DSP Datasheet(PDF) 63 Page - Renesas Technology Corp |
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R5F211B2DSP Datasheet(HTML) 63 Page - Renesas Technology Corp |
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63 / 339 page ![]() R8C/1A Group, R8C/1B Group 7. Voltage Detection Circuit Rev.1.30 Dec 08, 2006 Page 47 of 315 REJ09B0252-0130 Figure 7.4 Registers VCA1 and VCA2 Voltage Detection Register 1 Symbol Address After Reset(2) VCA1 0031h 00001000b Bit Symbol Bit Name Function RW NOTES : 1. 2. The VCA13 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled). The VCA13 bit is set to 1 (VCC ≥ Vdet 2) w hen the VCA27 bit in the VCA2 register is set to 0 (voltage detection 2 circuit disabled). — (b7-b4) Reserved bits Set to 0. RW Set to 0. 0 b7 b6 b5 b4 b3 b2 b1 b0 0000 The softw are reset, w atchdog timer reset, and voltage monitor 2 reset do not affect this register. VCA13 Voltage detection 2 signal monitor flag(1) 00 — (b2-b0) RW 0 : VCC < Vdet2 1 : VCC ≥ Vdet2 or voltage detection 2 circuit disabled RO Reserved bits Voltage Detection Register 2 (1) After Reset(4) Symbol Address Hardw are reset : 00h VCA2 0032h Pow er-on reset, voltage monitor 1 reset : 01000000b Bit Symbol Bit Name Function RW NOTES : 1. 2. 3. 4. Set the PRC3 bit in the PRCR register to 1 (w rite enable) before w riting to this register. To use the voltage monitor 1 reset, set the VCA26 bit to 1. After the VCA26 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting operation. To use the voltage monitor 2 interrupt/reset or the VCA13 bit in the VCA1 register, set the VCA27 bit to 1. After the VCA27 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting operation. Softw are reset, w atchdog timer reset, and voltage monitor 2 reset do not affect this register. VCA27 Voltage detection 2 enable bit(3) 0 : Voltage detection 2 circuit disabled 1 : Voltage detection 2 circuit enabled RW VCA26 Voltage detection 1 enable bit(2) 0 : Voltage detection 1 circuit disabled 1 : Voltage detection 1 circuit enabled RW — (b5-b0) Reserved bits Set to 0. RW 0000 00 b3 b2 b1 b0 b7 b6 b5 b4 |
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