R5F211B2DSP datasheet(64/339 Pages) RENESAS

64 / 339 page

R8C/1A Group, R8C/1B Group

7. Voltage Detection Circuit

Rev.1.30

Dec 08, 2006

Page 48 of 315

REJ09B0252-0130

Figure 7.5

VW1C Register

Voltage Monitor 1 Circuit Control Register

(1)

Symbol

Address

After Reset(2)

VW1C

0036h

Hardw are reset : 0000X000b

Pow er-on reset, voltage monitor 1 reset :

0100X001b

Bit Symbol

Bit Name

Function

NOTES :

Set the PRC3 bit in the PRCR register to 1 (w rite enable) before w riting to this register.

When rew riting the VW1C register, the VW1C2 bit may be set to 1. Set the VW1C2 bit to 0 after rew riting the VW1C

The value remains unchanged after a softw are reset, w atchdog timer reset, or voltage monitor 2 reset.

The VW1C0 bit is enabled w hen the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit

enabled). Set the VW1C0 bit to 0 (disable), w hen the VCA26 bit is set to 0 (voltage detection 1 circuit disabled).

VW1C7

Voltage monitor 1 reset generation

condition select bit

When the VW1C1 bit is set to 1 (digital filter

disabled mode), set to 1.

VW1C6

Voltage monitor 1 circuit mode

select bit

When the VW1C0 bit is set to 1 (voltage

monitor 1 reset enabled), set to 1.

—

(b3)

Reserved bit

VW1F1

Sampling clock select bits

b5 b4

0 0 : fRING-S divided by 1

0 1 : fRING-S divided by 2

1 0 : fRING-S divided by 4

1 1 : fRING-S divided by 8

VW1F0

When read, the content is undefined.

0 : Digital filter enabled mode

(digital filter circuit enabled)

1 : Digital filter disabled mode

(digital filter circuit disabled)

VW1C2

Reserved bit

VW1C1

Voltage monitor 1 digital filter

disable mode select bit

VW1C0

Voltage monitor 1 reset enable

bit(3)

0 : Disable

1 : Enable

b7 b6 b5 b4 b3 b2

Set to 0.

b1 b0

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