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R5F211B2DSP Datasheet(PDF) 71 Page - Renesas Technology Corp |
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R5F211B2DSP Datasheet(HTML) 71 Page - Renesas Technology Corp |
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71 / 339 page ![]() R8C/1A Group, R8C/1B Group 8. Processor Mode Rev.1.30 Dec 08, 2006 Page 55 of 315 REJ09B0252-0130 8. Processor Mode 8.1 Processor Modes Single-chip mode can be selected as the processor mode. Table 8.1 lists Features of Processor Mode. Figure 8.1 shows the PM0 Register and Figure 8.2 shows the PM1 Register. Figure 8.1 PM0 Register Table 8.1 Features of Processor Mode Processor Mode Accessible Areas Pins Assignable as I/O Port Pins Single-chip mode SFR, internal RAM, internal ROM All pins are I/O ports or peripheral function I/O pins. Processor Mode Register 0 (1) Symbol Address After Reset PM0 0004h 00h Bit Symbol Bit Name Function RW NOTE : 1. b3 b2 — b1 b0 00 0 — (b2-b0) b7 b6 b5 b4 RW Reserved bits Set to 0. Set the PRC1 bit in the PRCR register to 1 (w rite enable) before rew riting the PM0 register. The MCU is reset w hen this bit is set to 1. When read, the content is 0. RW — (b7-b4) PM03 Softw are reset bit Nothing is assigned. If necessary, set to 0. When read, the content is 0. |
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