R5F211B2DSP datasheet(69/339 Pages) RENESAS

69 / 339 page

R8C/1A Group, R8C/1B Group

7. Voltage Detection Circuit

Rev.1.30

Dec 08, 2006

Page 53 of 315

REJ09B0252-0130

7.3

Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset

Table 7.3 lists the Setting Procedure of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Associated Bits.

Figure 7.9 shows an Operating Example of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset. To use

voltage monitor 2 interrupt or voltage monitor 2 reset to exit stop mode, set the VW2C1 bit in the VW2C register to

1 (digital filter disabled).

NOTES:

1. Set the VW2C7 bit to 1 (when VCC reaches Vdet2 or below) for the voltage monitor 2 reset.

2. When the VW2C0 bit is set to 0 (disabled), steps 3, 4 and 5 can be executed simultaneously (with 1

instruction).

Table 7.3

Setting Procedure of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset

Associated Bits

Step

When Using Digital Filter

When Not Using Digital Filter

Voltage Monitor 2

Interrupt

Voltage Monitor 2

Reset

Voltage Monitor 2

Interrupt

Voltage Monitor 2

Reset

Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled).

Wait for td(E-A)

3(2)

Select the sampling clock of the digital filter

by bits VW2F0 to VW2F1 in the VW2C

Select the timing of the interrupt and reset

request by the VW2C7 bit in the VW2C

4(2)

Set the VW2C1 bit in the VW2C register to 0

(digital filter enabled).

Set the VW2C1 bit in the VW2C register to 1

(digital filter disabled).

5(2)

Set the VW2C6 bit in

the VW2C register to

0 (voltage monitor 2

interrupt mode).

Set the VW2C6 bit in

the VW2C register to

1 (voltage monitor 2

reset mode).

Set the VW2C6 bit in

the VW2C register to

0 (voltage monitor 2

interrupt mode).

Set the VW2C6 bit in

the VW2C register to

1 (voltage monitor 2

reset mode).

Set the VW2C2 bit in the VW2C register to 0 (passing of Vdet2 is not detected).

Set the CM14 bit in the CM1 register to 0

(low-speed on-chip oscillator on).

−

Wait for 4 cycles of the sampling clock of the

digital filter

− (No wait time)

Set the VW2C0 bit in the VW2C register to 1 (voltage monitor 2 interrupt/reset enabled).

R5F211B2DSP Datasheet(PDF) 69 Page - Renesas Technology Corp

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