R5F211B2DSP datasheet(84/339 Pages) RENESAS

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R8C/1A Group, R8C/1B Group

10. Clock Generation Circuit

Rev.1.30

Dec 08, 2006

Page 68 of 315

REJ09B0252-0130

10.4

Power Control

There are three power control modes. All modes other than wait mode and stop mode are referred to as standard

operating mode.

10.4.1

Standard Operating Mode

Standard operating mode is further separated into four modes.

In standard operating mode, the CPU clock and the peripheral function clock are supplied to operate the CPU

and the peripheral function clocks. Power consumption control is enabled by controlling the CPU clock

frequency. The higher the CPU clock frequency, the more processing power increases. The lower the CPU

clock frequency, the more power consumption decreases. When unnecessary oscillator circuits stop, power

consumption is further reduced.

Before the clock sources for the CPU clock can be switched over, the new clock source needs to be oscillating

and stable. If the new clock source is the main clock, allow sufficient wait time in a program until oscillation is

stabilized before exiting.

NOTE:

1. The low-speed on-chip oscillator is used as the on-chip oscillator clock when the CM14 bit in the

CM1 register is set to 0 (low-speed on-chip oscillator on) and the HRA01 bit in the HRA0 register is

set to 0. The high-speed on-chip oscillator is used as the on-chip oscillator clock when the HRA00

bit in the HRA0 register is set to 1 (high-speed on-chip oscillator A on) and the HRA01 bit in the

HRA0 register is set to 1.

Table 10.2

Settings and Modes of Clock Associated Bits

Modes

OCD Register

CM1 Register

CM0 Register

OCD2

CM17, CM16

CM13

CM06

CM05

High-speed mode

00b

Medium-

speed mode

Divide-by-2

01b

Divide-by-4

10b

Divide-by-8

−

Divide-by-16

11b

High-speed

and low-speed

on-chip

oscillator

modes(1)

No division

00b

−

Divide-by-2

01b

−

Divide-by-4

10b

−

Divide-by-8

−−

−

Divide-by-16

11b

−

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