HD6417618 datasheet(505/646 Pages) RENESAS

Part #	HD6417618

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

PDF	646 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 18 User Break Controller (UBC)

Rev. 6.00 Jun. 12, 2007 Page 473 of 610

REJ09B0131-0600

18.2

The user break controller has the following registers. For details on register addresses and access

sizes, refer to section 20, List of Registers.

• Break address register A (BARA)

• Break address mask register A (BAMRA)

• Break bus cycle register A (BBRA)

• Break address register B (BARB)

• Break address mask register B (BAMRB)

• Break bus cycle register B (BBRB)

• Break data register B (BDRB)

• Break data mask register B (BDMRB)

• Break control register (BRCR)

• Execution times break register (BETR)

• Branch source register (BRSR)

• Branch destination register (BRDR)

18.2.1

Break Address Register A (BARA)

BARA is a 32-bit readable/writable register. BARA specifies the address used for a break

condition in channel A.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 0

BAA31 to

BAA 0

All 0

R/W

Break Address A

Store the address on the LAB or IAB specifying break

conditions of channel A.

HD6417618 Datasheet(PDF) 505 Page - Renesas Technology Corp