R5F3640DDFB datasheet(63/398 Pages) RENESAS

63 / 398 page

REJ09B0392-0064 Rev.0.64

Oct 12, 2007

Page 42 of 373

Under development

Preliminary Specification

Specification in this preliminary version is subject to change.

M16C/64 Group

6. Voltage Detection Circuit

Figure 6.6

Brown-out Reset Operation Example

6.2

Low Voltage Detection Interrupt

If the D40 bit in the D4INT register is set to 1 (low voltage detection interrupt enabled), the low voltage

detection interrupt request is generated when the voltage applied to the VCC1 pin is above or below

Vdet2. The low voltage detection interrupt shares the same interrupt vector with the watchdog timer inter-

rupt, oscillation stop, and re-oscillation detection interrupt.

Set the D41 bit in the D4INT register to 1 (enabled) to use the low voltage detection interrupt to exit stop

mode.

The D42 bit in the D4INT register is set to 1 as soon as the voltage applied to the VCC1 pin reaches

Vdet2 due to the voltage rise and voltage drop. When the D42 bit changes 0 to 1, the low voltage detec-

tion interrupt request is generated. Set the D42 bit to 0 by program. However, when the D41 bit is set to 1

and the microcomputer is in stop mode, the low voltage detection interrupt request is generated regard-

less of the D42 bit state if the voltage applied to the VCC1 pin is detected to be above Vdet2. The micro-

computer then exits stop mode.

Table 6.2 shows Low Voltage Detection Interrupt Request Generation Conditions.

Bits DF1 to DF0 in the D4INT register determine the sampling period that detects the voltage applied to

the VCC1 pin reaches Vdet2. Table 6.3 shows the Sampling Periods.

Vdet0

Internal reset signal

VCC

The above diagram shows an instance in which the following conditions are all met.

•The VC25 bit in the VCR2 register = 1 (voltage detection 0 circuit enabled)

•The VW0C0 bit in the VW0C register = 1 (brown-out reset enabled)

Pins, the CPU, and SFRs are initialized when the internal reset signal becomes low.

The microcomputer executes the program in an address indicated by the reset vector when the internal reset signal changes low

to high.

Refer to 4. SFRs for the SFR status after reset.

fOCO-S ×32

Digital filter sampling clock

×4 cycles

When the VW0C1 bit is 0

(digital filter enabled)

Internal reset signal

When the VW0C1 bit is 1

(digital filter disabled)

fOCO-S×

VW0C1 = the bit in the VW0C register

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