R5F3640DDFB datasheet(78/398 Pages) RENESAS

78 / 398 page

REJ09B0392-0064 Rev.0.64

Oct 12, 2007

Page 57 of 373

Under development

Preliminary Specification

Specification in this preliminary version is subject to change.

M16C/64 Group

8. Bus

8.2.4

Read and Write Signals

When the data bus is 16 bits wide, the read and write signals can be chosen to be a combination of

RD,

BHE, and, WR or a combination of RD, WRL, and WRH by using the PM02 bit in the PM0 register.

When the data bus is 8 bits wide, use a combination of

RD, WR, and BHE.

Table 8.3 shows the Operation of

RD, WRL, and WRH Signals. Table 8.4 shows the Operation of RD,

WR, and BHE Signals.

NOTE:

Do not use.

8.2.5

ALE Signal

The ALE signal latches the address when accessing the multiplexed bus space. Latch the address

when the ALE signal falls.

Figure 8.3

ALE Signal, Address Bus, Data Bus

Table 8.3

Operation of

RD, WRL, and WRH Signals

Data Bus Width

WRL

WRH

Status of External Data Bus

16-bit

(BYTE pin input = “L”)

Read data

Write 1 byte of data to an even address

Write 1 byte of data to an odd address

Write data to both even and odd addresses

Table 8.4

Operation of

RD, WR, and BHE Signals

Data Bus

Width

BHE

Status of External Data Bus

16-bit

(BYTE pin

input = “L”)

Write 1 byte of data to an odd address

Read 1 byte of data from an odd address

Write 1 byte of data to an even address

Read 1 byte of data from an even address

Write data to both even and odd addresses

Read data from both even and odd addresses

8-bit

(BYTE pin

input = “H”)

− (1)

H or L Write 1 byte of data

− (1)

H or L Read 1 byte of data

When BYTE pin input = “H”

When BYTE pin input = “L”

ALE

Address

Data

Address (1)

A0/D0 to A7/D7

A8 to A19

ALE

Address

Data

Address

A1/D0 to A8/D7

A9 to A19

Address

NOTE :

If the entire CS space is assigned a multiplexed bus, these pins function as I/O ports.

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