R5F3640DDFB datasheet(69/398 Pages) RENESAS

69 / 398 page

REJ09B0392-0064 Rev.0.64

Oct 12, 2007

Page 48 of 373

Under development

Preliminary Specification

Specification in this preliminary version is subject to change.

M16C/64 Group

7. Processor Mode

Figure 7.1

PM0 Register

b7 b6 b5 b4

Processor Mode Register 0 (1)

Symbol

PM0

Address

0004h

Bit Symbol

Bit Name

PM00

After Reset (4)

00000000b (CNVSS pin = “L”)

00000011b (CNVSS pin = “H”)

1. Write to this register after setting the PRC1 bit in the PRCR register to 1 (write enabled).

2. Bits PM02, and PM04 to PM07 are effective when bits PM01 and PM00 are set to 01b (memory expansion mode) or 11b

(microprocessor mode).

3. To set bits PM01 and PM00 to 01b and bits PM05 and PM04 to 11b (multiplexed bus assigned to the entire CS space),

apply an “H” signal to the BYTE pin (external data bus is 8 bits wide). While the CNVSS pin is held “H” (= VCC1), do not

rewrite the PM05 and PM04 bits to 11b after reset. If bits PM05 and PM04 are set to 11b during memory expansion

mode, P3_1 to P3_7 and P4_0 to P4_3 become I/O ports, in which case the accessible area for each CS is 256 bytes.

4. Bits PM01 and PM00 do not change at software reset, watchdog timer reset, and oscillation stop detection reset.

Function

b1 b0

0 : Single-chip mode

1 : Memory expansion mode

0 : Do not set

1 : Microprocessor mode

Processor mode bit (4)

PM01

PM02

R/W mode select bit (2)

0 : RD, BHE, WR

1 : RD, WRH, WRL

PM03

Software reset bit

Setting this bit to 1 resets the

microcomputer. Read as 0

BCLK output disable bit (2)

PM07

0 : BCLK is output

1 : BCLK is not output

(pin is left high-impedance)

PM06

Port P4_0 to P4_3 function

select bit (2)

0 : Address output

1 : Port function (address is not output)

PM04

Multiplexed bus space select

bit (2)

b5 b4

0 : Multiplexed bus is unused

(separate bus in the entire CS space)

1 : Allocated to CS2 space

0 : Allocated to CS1 space

1 : Allocated to the entire CS space (3)

PM05

NOTES :

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