R5F3640DDFB datasheet(82/398 Pages) RENESAS

82 / 398 page

REJ09B0392-0064 Rev.0.64

Oct 12, 2007

Page 61 of 373

Under development

Preliminary Specification

Specification in this preliminary version is subject to change.

M16C/64 Group

8. Bus

8.2.9

External Bus Status When Internal Area IS Accessed

Table 8.7 shows the External Bus Status When Internal Area Accessed.

8.2.10

Software Wait

The PM17 bit in the PM1 register, which is a software-wait-related bit, has an influence over the internal

memory and the external area.

The SFR area is accessed in 2 BCLK or 3 BCLK cycles as determined by the PM20 bit in the PM2 reg-

ister. Data flash, one of the internal ROMs, is affected by the PM17 bit and the FMR17 bit in the FMR1

for details.

Software waits can be inserted to the external area by setting the PM17 bit or setting the CSiW bit in the

CSR register or bits CSEi1W to CSEi0W in the CSE register for each CSi (i = 0 to 3). To use the

RDY

signal, set the corresponding CSiW bit to 0 (with wait state). Refer to Table 8.9 “Bits and Bus Cycles

Related to Software Wait (External Area)”

for details.

Table 8.8 shows the Bits and Bus Cycles Related to Software Wait (SFR, Internal Memory), Figure 8.6

shows the CSE register, and Table 8.9 shows the Bits and Bus Cycles Related to Software Wait (Exter-

nal Area).

NOTES:

The PM 20 bit is valid when the PLC07 bit in the PLC0 register is set to 1 (PLL operation).

When 2.7 V

≤ VCC1 ≤ 3.0 V and f (BCLK) ≥ 16 MHz, or when 3.0 V < VCC1 ≤ 5.5 V and f (BCLK) ≥

20 MHz, 1 wait is necessary to read data flash. Use the PM17 bit or the FMR 17 bit to set 1 wait.

Status after reset.

Table 8.7

External Bus Status When Internal Area Accessed

Item

SFR Accessed

Internal ROM, RAM Accessed

A0 to A19

Address output

Maintain the last accessed address of

external area or SFR

D0 to D15

When Read

High-impedance

When Write

Output data

Undefined

RD, WR, WRL, WRH

RD, WR, WRL, WRH output

Output “H”

BHE

BHE output

Maintain the last accessed status of exter-

nal area or SFR

CS0 to CS3

Output “H”

ALE

Output “L”

Table 8.8

Bits and Bus Cycles Related to Software Wait (SFR, Internal Memory)

Area

Setting of Software-Wait-related Bits

Soft-

ware

Wait

Bus cycle

PM2 Register

PM20 Bit (1)

FMR1 Register

FMR17 Bit

PM1 Register

PM17 Bit

SFR

--1 wait

2 BCLK cycles(3)

2 waits 3 BCLK cycles

Internal

RAM

No wait 1 BCLK cycle(3)

1 wait

2 BCLK cycles

Internal

ROM

Program ROM 1

Program ROM 2

No wait 1 BCLK cycle(3)

1 wait

2 BCLK cycles

Data Flash (2)

-0

1 wait

2 BCLK cycles(3)

No wait 1 BCLK cycle

1 wait

2 BCLK cycle

− indicates that either 0 or 1 can be set.

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