SH7021 datasheet(77/509 Pages) RENESAS

77 / 509 page

RENESAS 57

4.6

Cases in Which Exceptions Are Not Accepted

In some cases, address errors and interrupts that directly follow a delayed branch instruction or

interrupt-disabled instruction are not accepted immediately. Table 4.9 lists these cases. When this

occurs, the exception is accepted when an instruction that can accept the exception is decoded.

Table 4.9

Cases in Which Exceptions Are Not Accepted

Exception Source

Case

Address Error

Interrupt

Immediately after delayed branch instruction*1

Immediately after interrupt-disabled instruction*2

X: Not accepted

O: Accepted

Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE

2. Interrupt-disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, STS.L

4.6.1

Immediately after Delayed Branch Instructions

Address errors and interrupts are not accepted when an instruction in a delay slot immediately

following a delayed branch instruction is decoded. The delayed branch instruction and the

instruction in the delay slot are therefore always executed one after the other. Exception

processing is never inserted between them.

4.6.2

Immediately after Interrupt-Disabling Instructions

Interrupts are not accepted when the instruction immediately following an interrupt-disabled

instruction is decoded. Address errors are accepted, however.

SH7021 Datasheet(PDF) 77 Page - Renesas Technology Corp