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5.1.3

Pin Configuration

INTC pins are summarized in table 5.1.

Table 5.1

INTC Pin Configuration

Name

Abbr.

I/O

Function

Nonmaskable interrupt input

NMI

Inputs a non-maskable interrupt request

signal

Interrupt request input pins

IRQ0–IRQ7

Inputs maskable interrupt request signals

Interrupt request output pin

IRQOUT

Outputs a signal indicating an interrupt

source has occurred.

5.1.4

Registers

The interrupt controller has six registers as listed in table 5.2. These registers are used for setting

interrupt priority levels and controlling the detection of external interrupt input signals.

Table 5.2

Interrupt Controller Register Configuration

Name

Abbr.

R/W

Address*2

Initial Value

Bus width

Interrupt priority register A

IPRA

R/W

H'5FFFF84

H'0000

8, 16, 32

Interrupt priority register B

IPRB

R/W

H'5FFFF86

H'0000

8, 16, 32

Interrupt priority register C

IPRC

R/W

H'5FFFF88

H'0000

8, 16, 32

Interrupt priority register D

IPRD

R/W

H'5FFFF8A

H'0000

8, 16, 32

Interrupt priority register E

IPRE

R/W

H'5FFFF8C

H'0000

8, 16, 32

Interrupt control register

ICR

R/W

H'5FFFF8E

8, 16, 32

Note:

1. H'8000 when pin NMI is high, H'0000 when pin NMI is low.

2. Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For

details on the register addresses, see section 8.3.5, Description of Areas.

5.2

Interrupt Sources

There are four types of interrupt sources: NMI, user break, IRQ, and on-chip peripheral module

interrupts.

Interrupt rankings are expressed as priority levels (0–16), with 0 the lowest and 16 the highest. An

interrupt set to level 0 is masked.

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