SH7021 datasheet(16/509 Pages) RENESAS

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10.3

CPU Interface .................................................................................................................... 241

10.3.1 16-Bit Accessible Registers.................................................................................. 241

10.3.2 8-Bit Accessible Registers.................................................................................... 243

10.4

Description of Operation ................................................................................................... 244

10.4.1 Overview .............................................................................................................. 244

10.4.2 Basic Functions .................................................................................................... 245

10.4.3 Synchronizing Mode ............................................................................................ 256

10.4.4 PWM Mode .......................................................................................................... 258

10.4.5 Reset-Synchronized PWM Mode ......................................................................... 262

10.4.6 Complementary PWM Mode................................................................................ 264

10.4.7 Phase Counting Mode .......................................................................................... 272

10.4.8 Buffer Mode ......................................................................................................... 274

10.4.9 ITU Output Timing .............................................................................................. 280

10.5

Interrupts............................................................................................................................ 281

10.5.1 Timing of Setting Status Flags ............................................................................. 281

10.5.2 Clear Timing of Status Flags................................................................................ 283

10.5.3 Interrupt Sources and Activating the DMAC ....................................................... 284

10.6

Notes and Precautions........................................................................................................ 285

10.6.1 Contention between TCNT Write and Clear........................................................ 285

10.6.2 Contention between TCNT Word Write and Increment ...................................... 286

10.6.3 Contention between TCNT Byte Write and Increment........................................ 287

10.6.4 Contention between GR Write and Compare Match............................................ 288

10.6.5 Contention between TCNT Write and Overflow/Underflow ............................... 289

10.6.6 Contention between General Register Read and Input Capture ........................... 290

10.6.7 Contention Between Counter Clearing by Input Capture and Counter

Increment.............................................................................................................. 291

10.6.8 Contention between General Register Write and Input Capture.......................... 292

10.6.9 Note on Waveform Cycle Setting ........................................................................ 292

10.6.10 Contention Between BR Write and Input Capture ............................................... 293

10.6.11 Note on Writing in the Synchronizing Mode ....................................................... 294

10.6.12 Note on Setting Reset-synchronized PWM Mode/Complementary

PWM Mode .......................................................................................................... 294

10.6.13 Clearing the Complementary PWM Mode........................................................... 295

10.6.14 ITU Operating Modes .......................................................................................... 295

Section 11 Programmable Timing Pattern Controller (TPC) ............................... 303

11.1

Overview............................................................................................................................ 303

11.1.1 Features ................................................................................................................ 303

11.1.2 Block Diagram...................................................................................................... 304

11.1.3 Input/Output Pins.................................................................................................. 305

11.1.4 Registers ............................................................................................................... 306

11.2

Register Descriptions......................................................................................................... 306

11.2.1 Port B Control Registers 1 and 2 (PBCR1, PCBR2)............................................ 306

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