R8C13 datasheet(67/224 Pages) RENESAS

67 / 224 page

Rev.1.20

Jan 27, 2006

page 56 of 205

REJ09B0111-0120

R8C/13 Group

Interrupt factors

Level that is set to IPL

Watchdog timer, oscillation stop detection, voltage detection

Software, address match, single-step

Not changed

• Variation of IPL when Interrupt Request is Accepted

When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is

set in the IPL.

When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels

listed in Table 10.5 is set in the IPL. Shown in Table 10.5 are the IPL values of software and special

interrupts when they are accepted.

Table 10.5 IPL Level That Is Set to IPL When A Software or Special Interrupt Is Accepted

Figure 10.5 Interrupt Response Time

• Interrupt Response Time

Figure 10.5 shows the interrupt response time. The interrupt response or interrupt acknowledge time

denotes a time from when an interrupt request is generated till when the first instruction in the inter-

rupt routine is executed. Specifically, it consists of a time from when an interrupt request is gener-

ated till when the instruction then executing is completed (see #a in Figure 10.5) and a time during

which the interrupt sequence is executed (20 cycles, see #b in Figure 10.5).

Instruction

Interrupt sequence

Instruction in

interrupt routine

Time

Interrupt response time

(a)

20 cycles (b)

Interrupt request acknowledged

Interrupt request generated

(a) A time from when an interrupt request is generated till when the instruction then

executing is completed. The length of this time varies with the instruction being

executed. The DIVX instruction requires the longest time, which is equal to 30 cycles

(without wait state, the divisor being a register).

(b) 21 cycles for address match and single-step interrupts.

10.1 Interrupt Overview

R8C13 Datasheet(PDF) 67 Page - Renesas Technology Corp