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R8C13 Datasheet(PDF) 86 Page - Renesas Technology Corp

Part # R8C13
Description  16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY/R8C/Tiny SERIES
PDF  224 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R8C13 Datasheet(HTML) 86 Page - Renesas Technology Corp

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Rev.1.20
Jan 27, 2006
page 75 of 205
REJ09B0111-0120
R8C/13 Group
12.1.3 Event Counter Mode
In this mode, the timer counts an external signal fed to INT1/CNTR0 pin (See “Table 12.4 Event
Counter Mode Specifications”). Figure 12.6 shows TXMR register in event counter mode.
Item
Specification
Count source
External signals fed to CNTR0 pin (Active edge is selected by program)
Count operation
• Down count
• When the timer underflows, the contents in the reload register is reloaded and the count
is contiuned.
Divide ratio
1/(n+1)(m+1)
n: set value of PREX register, m: set value of TX register
Count start condition
Write “1” (count start) to TXS bit in TXMR register
Count stop condition
Write “0” (count stop) to TXS bit in TXMR register
Interrupt request
• When Timer X underflows [Timer X interrupt]
generation timing
INT1/CNTR0 pin function
_______
Count source input (INT1 interrupt input)
CNTR0 pin function
Programmable I/O port
Read from timer
Count value can be read by reading TX register
Same applies to PREX register.
Write to timer
Value written to TX register is written to both reload register and counter.
Same applies to PREX register.
Select function
• INT1/CNTR0 polarity switching function
Active edge of count source can be selected with R0EDG.
Timer X mode register
Symbol
Address
After reset
TXMR
008B16
0016
Bit name
Function
Bit symbol
RW
b7 b6 b5 b4 b3 b2 b1 b0
1 0 : Event counter mode
b1 b0
TXMOD2
TXS
TXMOD1
R0EDG
TXMOD0
TXOCNT
Operation mode
select bit 0, 1
Timer X count
start flag
0 : Stops counting
1 : Starts counting
0
0
Set to "0" in event counter mode
0 : Rising edge
1 : Falling edge
0
TXEDG
TXUND
RW
RW
RW
RW
RW
RW
RW
RW
INT1/CNTR0 polarity
switching bit(1)
Set to "0" in event counter mode
Set to "0" in event counter mode
NOTES:
1. The IR bit in the INT1IC register may be set to “1” (interrupt requested) when the R0EDG bit is rewritten.
Refer to the paragraph 19.2.5 “Changing Interrupt Factor” in the Usage Notes Reference Book.
00
1
Set to "0" in event counter mode
Figure 12.6 TXMR Register in Event Counter Mode
Table 12.4 Event Counter Mode Specifications
12.1 Timer (Timer X)



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