7721 datasheet(111/577 Pages) RENESAS

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7721 Group User’s Manual

INTERRUPTS

7–14

7.7 Sequence from acceptance of interrupt request until execution of interrupt routine

Fig. 7.7.2 INTACK sequence timing (at minimum)

[S]H

qWhen stack pointer (S)’s contents are even and no Wait

PCH

([S]–1)H

FF16

ADH

PCH

PSH

FF16

Interrupt

disable

flag (I)

Internal

clock

CPU

PCL

PSL

XX16

ADH

ADL

PCL

XX16

ADL

[S]L

INTACK sequence

Op-code

: Not used

[S]

XX16

AD H

AD L

: Contents of stack pointer (S)

: Low-order 8 bits of vector address

: Contents of vector address (High-order address)

: Contents of vector address (Low-order address)

CPU

D H

([S]–2)H ([S]–3)H ([S]–4)H ([S]–5)H ([S]–5)H

([S]–1)L ([S]–2)L ([S]–3)L ([S]–4)L ([S]–5)L ([S]–5)L

: CPU standard clock

: High-order 8 bits of CPU internal address bus

: Middle-order 8 bits of CPU internal address bus

: Low-order 8 bits of CPU internal address bus

: CPU internal data bus for odd address

: CPU internal data bus for even address

7.7.1 Change in IPL at acceptance of interrupt request

When an interrupt request is accepted, the processor interrupt priority level (IPL) is replaced with the

interrupt priority level of the accepted interrupt. This results in easy control of the processing for multiple

interrupts. (Refer to section “7.9 Multiple interrupts.”)

At reset or when a watchdog timer interrupt or a software interrupt is accepted, a value listed in Table 7.7.1

is set into the IPL.

Table 7.7.1 Change in IPL at acceptance of interrupt request

Interrupts

Reset

Watchdog timer

Zero division

BRK instruction

Other interrupts

Change in IPL

Level 0 (“0002”) is set.

Level 7 (“1112”) is set.

Not changed.

Accepted interrupt priority level is set.

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