TDA9109A datasheet(28/47 Pages) STMICROELECTRONICS

28 / 47 page

TDA9109A

28/47

1.6 Sync Identification Status

The MCU can read (address read mode: 8D) the

status register via the I

2C bus, and then select the

sync priority depending on this status.

Among other data this register indicates the pres-

ence of sync pulses on H/HVIN, VSYNCIN and

(when 12 V is supplied) whether a Vext has been

extracted from H/HVIN. Both horizontal and verti-

cal sync are detected even if only 5 V is supplied.

In order to choose the right sync priority the MCU

may proceed as follows (see I

2C Address Table):

• refresh the status register

• wait at least for 20ms (Max. vertical period)

• read this status register

Sync priority choice should be:

Of course, when the choice is made, we can re-

fresh the sync detections and verify that the ex-

tracted Vsync is present and that no sync type

change has occurred. The sync processor also

gives sync polarity information.

1.7 IC status

The IC can inform the MCU about the 1st horizon-

tal PLL and vertical section status (locked or not)

and about the XRAY protection (activated or

not).Resetting the XRAY internal latch can be

done either by decreasing the VCC supply or di-

rectly resetting it via the I2C interface.

1.8 Sync Inputs

Both H/HVIN and VSYNCIN inputs are TTL com-

patible triggers with hysteresis to avoid erratic de-

tection. Both inputs include a pull up resistor con-

nected to VDD.

1.9 Sync Processor Output

The sync processor indicates on the D8 bit of the

status register whether 1st PLL is locked to an in-

coming horizontal sync. Its level goes to low when

locked. This information is also available on pin 3

when sub-address 02 D8 is equal to 1. When PLL1

is unlocked, pin 3 output voltage goes to 5V.

2 HORIZONTAL PART

2.1 Internal Input Conditions

A digital signal (horizontal sync pulse or TTL com-

posite) is sent by the sync processor to the hori-

zontal input. It may be positive or negative (see

Figure 5).

Using internal integration, both signals are recog-

nized if Z/T < 25%. Synchronization occurs on the

leading edge of the internal sync signal.

The minimum value of Z is 0.7

µs.

Another integration is able to extract the vertical

pulse from composite sync if the duty cycle is high-

er than 25% (typically d = 35%),

(see Figure 6).

Vextd

det

Sync

priority

Subaddress

03 (D8)

Comment

Sync type

Yes

Separated H&V

Yes

Composite TTL H&V

TDA9109A Datasheet(PDF) 28 Page - STMicroelectronics

TDA9109A Datasheet(HTML) 28 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

Datasheet Download

Link URL