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TDA9109A Datasheet(PDF) 35 Page - STMicroelectronics

Part # TDA9109A
Description  LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR
PDF  47 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

TDA9109A Datasheet(HTML) 35 Page - STMicroelectronics

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Figure 16. AGC Loop Block Diagram
3.4 Basic Equations
In first approximation, the amplitude of the ramp
on Pin 23 (VOUT) is:
VOUT - VPOS = (VOSC -VDCMID)
. (1 + 0.3 (V
AMP))
where:
VDCMID = 7/16 VREF (middle value of the ramp on
Pin 22, typically 3.6V)
VOSC =V22 (ramp with fixed amplitude)
VAMP = -1 for minimum vertical amplitude register
value and +1 for maximum
VPOS is calculated by:
VPOS = VDCMID + 0.4 VP
where VP = -1 for minimum vertical position regis-
ter value and +1 for maximum.
The current available on Pin 22 is:
IOSC =
. V
REF
. C
OSC
. f
where COSC = capacitor connected on Pin 22 and
f = synchronization frequency.
Geometric Corrections
The principle is represented in Figure 17.
Starting from the vertical ramp, a parabola-shaped
current is generated for E/W correction (also
known as Pin Cushion correction), dynamic hori-
zontal phase control correction, and vertical dy-
namic focus correction.
The parabola generator is made by an analog mul-
tiplier, the output current of which is equal to:
∆I= k . (VOUT - VDCMID)
2
where VOUT is the vertical output ramp (typically
between 2 and 5V) and VDCMID is 3.6V
(for VREF-V = 8.2V). The VOUT sawtooth is typical-
ly centered on 3.6V. By changing the vertical posi-
tion, the sawtooth shifts by
±0.4V.
To provide good screen geometry for any end user
adjustment, the TDA9109A has the “geometry
tracking” feature which allows generation of a dis-
symetric parabola depending on the vertical posi-
tion.
Due to the large output stage voltage range (E/W
Pin Cushion, Keystone, E/W Corner), the combi-
nation of the tracking function, maximum vertical
amplitude, maximum or minimum vertical position
and maximum gain on the DAC control may lead
to output stage saturation. This must be avoided
by limiting the output voltage with appropriate I
2C
register values.
VSYNCIN 2
Synchro
Polarity
Oscillator
Discharge.
22
OSC
CAP
Sampling
Sampling
Capacitance
S Correction
VS Amp
sub-add 07/7bits
Cor_C
sub-add 08/7bits
C Correction
18 BREATH
23 VOut
Vert. Amp
sub-.05/7bits
VMoiré
sub.0C/7bits
V Position
sub.06/7bits
Vlow
sawth
.
disch.
REF
Charge Current
Transconductance Amplifier
3
8



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